FPGA学习-9-ip核之ARM

你的名字 2022-01-11 05:37 294阅读 0赞

系统:win10  
软件编辑和程序下载平台:Quartus II  
仿真平台:modelsim  
FPGA:EP4CE6

## 1 创建生成RAM\_1port.qip的ip核文件,并添加到工程中 ##

1 点击tools魔法棒,创建IP核,找到RAM新建par\\ipcode  
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设置大小,8X32K,同时性能更好的是M9K型号,由于刚选择的是1port,这里就要选择第一个single lock  
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接下来配置缺省等  
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首先看一张图,用来解释ram尽量不要使用同时进行,一定要分开![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMyNDYwODE5_size_16_color_FFFFFF_t_70 3][]  
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这里主要选择对RAM是否初始化![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMyNDYwODE5_size_16_color_FFFFFF_t_70 5]  
next到最后一个  
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## 2 代码 ##

1 ram\_rw,v–这里主要是写的如何读写操作

module ram_rw(
        input               clk        ,  //时钟信号
        input               rst_n      ,  //复位信号，低电平有效
        
        output              ram_wr_en  ,  //ram写使能
        output              ram_rd_en  ,  //ram读使能
        output  reg  [4:0]  ram_addr   ,  //ram读写地址
        output  reg  [7:0]  ram_wr_data,  //ram写数据
        
        input        [7:0]  ram_rd_data   //ram读数据        
        );
    
    //reg define
    reg    [5:0]  rw_cnt ;                //读写控制计数器
    
    //*****************************************************
    //**                    main code
    //*****************************************************
    
    
    
    //先写后读
    //rw_cnt计数范围在0~31,ram_wr_en为高电平;32~63时,ram_wr_en为低电平
    assign  ram_wr_en = ((rw_cnt >= 6'd0) && (rw_cnt <= 6'd31))  ?  1'b1  :  1'b0;
    //rw_cnt计数范围在32~63,ram_rd_en为高电平;0~31时,ram_rd_en为低电平
    assign  ram_rd_en = ((rw_cnt >= 6'd32) && (rw_cnt <= 6'd63))  ?  1'b1  :  1'b0;
    
    //读写控制计数器,计数器范围0~63
    always @(posedge clk or negedge rst_n) begin
        if(rst_n == 1'b0)
            rw_cnt <= 6'd0;    
        else if(rw_cnt == 6'd63)
            rw_cnt <= 6'd0;
        else
            rw_cnt <= rw_cnt + 6'd1;    
    end    
    
    //读写控制器计数范围：0~31 产生ram写使能信号和写数据信号
    always @(posedge clk or negedge rst_n) begin
        if(rst_n == 1'b0)
            ram_wr_data <= 8'd0;  
        else if(rw_cnt >= 6'd0 && rw_cnt <= 6'd31)
            ram_wr_data <= ram_wr_data + 8'd1;
        else
            ram_wr_data <= 8'd0;         
    end    
    
    //读写地址信号 范围:0~31
    always @(posedge clk or negedge rst_n) begin
        if(rst_n == 1'b0)
            ram_addr <= 5'd0;
        else if(ram_addr == 5'd31)
            ram_addr <= 5'd0;
        else
            ram_addr <= ram_addr + 1'b1; 
    end
    
    endmodule

2 ip\_ram–这里是顶层文件,主要例化上个文件块

module ip_ram(
        input               sys_clk        ,  //系统时钟
        input               sys_rst_n         //系统复位，低电平有效
        );
    
    //wire define
    wire             ram_wr_en   ;  //ram写使能  
    wire             ram_rd_en   ;  //ram读使能  
    wire    [4:0]    ram_addr    ;  //ram读写地址 
    wire    [7:0]    ram_wr_data ;  //ram写数据  
    wire    [7:0]    ram_rd_data ;  //ram读数据  
    
    //*****************************************************
    //**                    main code
    //*****************************************************
    
    //ram读写模块
    ram_rw  u_ram_rw(
        .clk            (sys_clk),
        .rst_n          (sys_rst_n),
    
        .ram_wr_en      (ram_wr_en  ),
        .ram_rd_en      (ram_rd_en  ),
        .ram_addr       (ram_addr   ),
        .ram_wr_data    (ram_wr_data),
    
        .ram_rd_data    (ram_rd_data)
        );
    
    //ram ip核
    ram_1port  u_ram_1port(
        .address      (ram_addr),
        .clock        (sys_clk),
        .data         (ram_wr_data),
        .rden         (ram_rd_en),
        .wren         (ram_wr_en),
        .q            (ram_rd_data)
        );
    
    endmodule

## 3 接下来进行硬件仿真 ##

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仿真读写,  
先写0-31,读出来的也是0-31,成功

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