Verilog可综合FSM的实现

た入场券 2023-06-05 14:58 71阅读 0赞

**简介：**  
用Verilog实现一个具有4个状态的有限状态机。  
状态转移图如下：  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]  
**代码实现：**

/*----------------------------------------
    Filename: fsm.v
    Function: 具有4个状态的有限状态机(可综合)
    Author: Zhang Kaizhou
    Date: 2019-10-8 21:48:35
    -----------------------------------------*/
    module fsm(y3, y2, y1, state, clk, reset, a);
    	//定义输入输出端口
    	output y3, y2, y1;
    	output [3 : 0] state;
    	input clk, reset, a;
    	
    	//定义状态寄存器
    	reg y3, y2, y1;
    	reg [3 : 0] state;
    	
    	//状态编码
    	//parameter idle = 2'b00, start = 2'b01, stop = 2'b10, clear = 2'b11; //格雷码
    	parameter idle = 4'b1000, start = 4'b0100, stop = 4'b0010, clear = 4'b0001; //独热码(推荐)
    	
    	//状态转移
    	always@(posedge clk)
    	begin
    		if(!reset)
    		begin
    			state <= idle;
    			y3 = 0; y2 = 0; y1 = 0;
    		end
    		else
    		begin
    			case(state)
    				idle: if(a)
    						begin
    							state <= start;
    							y3 = 1; y2 = 1; y1 = 1;
    						end
    				start: if(!a)
    						begin
    							state <= stop;
    							y3 = 1; y2 = 0; y1 = 1;
    						end
    				stop: if(a)
    						begin
    							state <= clear;
    							y3 = 0; y2 = 1; y1 = 0;
    						end
    				clear: if(!a)
    						begin
    							state <= idle;
    						end
    				default: state <= idle;
    			endcase
    		end
    	end
    endmodule

/*---------------------------
    Filename: fsm_t.v
    Function: 有限状态机测试程序
    Author: Zhang Kaizhou
    Date: 2019-10-8 21:54:17
    ---------------------------*/
    `timescale 1ns/1ns
    `define PERIOD 5
    module fsm_t(y3, y2, y1, state);
    	output y3, y2, y1;
    	output [3 : 0] state;
    	reg clk, reset, a;
    	
    	fsm m0(.y3(y3), .y2(y2), .y1(y1), .state(state), .clk(clk), .reset(reset), .a(a));
    	
    	always
    	begin
    		clk = 0;
    		#`PERIOD clk = ~clk;
    	end
    	
    	initial
    	begin
    		#100 reset = 0; a = 0;
    		#100 reset = 1; a = 1;
    		#100 a = 0;
    		#100 a = 1;
    		#100 a = 0;
    		#500 $stop;
    	end
    endmodule

**ModelSim仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70 1]  
**总结：**  
由上面的仿真结果可知，以上的代码实现了FSM的目标逻辑功能。

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[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70 1]: /images/20230601/4bd3fde20b784d3ba39d6f51577f489b.png