Verilog 实现FSM(序列检测器1101)

偏执的太偏执、 2023-05-29 13:27 1阅读 0赞

**简介：**  
Verilog用一个有限状态机实现1101(可重叠)序列检测器，重点在于有限状态机三段式编码风格的实践。  
**代码实现：**

/*----------------------------------
    Filename: squence_detector.v
    Function: 检测序列1101(可重叠检测)
    Author: Zhang Kaizhou
    Date: 2019-11-6 15:06:46
    -----------------------------------*/
    module squence_detector(clk, reset, d, y);
    	//定义输入输出端口
    	input clk, reset, d;
    	output y;
    	
    	//内部寄存器及连线定义
    	reg [4 : 0] current_state, next_state;
    	wire y;
    	
    	//状态定义
    	parameter s0 = 5'b00000, s1 = 5'b00010, s2 = 5'b00100, s3 = 5'b01000, s4 = 5'b10000;
    	
    	//时序逻辑实现状态转移
    	always@(posedge clk or negedge reset)
    	begin
    		if(!reset) current_state <= s0;
    		else current_state <= next_state;
    	end
    	
    	//组合逻辑实现状态转移条件判断
    	always@(current_state or d)
    	begin
    		case(current_state)
    			s0: next_state = d ? s1 : s0;
    			s1: next_state = d ? s2 : s0;
    			s2: next_state = d ? s2 : s3;
    			s3: next_state = d ? s4 : s0;
    			s4: next_state = d ? s1 : s0;
    		endcase
    	end
    	
    	//组合逻辑实现输出
    	// always@(current_state)
    	// begin
    		// case(current_state)
    			// s0: y = 1'b0;
    			// s1: y = 1'b0;
    			// s2: y = 1'b0;
    			// s3: y = 1'b0;
    			// s4: y = 1'b1;
    		// endcase
    	// end
    	
    	//本例中由于只有一个输出，可用assign语句实现
    	assign y = (current_state == s4) ? 1 : 0;
    	
    endmodule

/*---------------------------------------
    Filename: squence_detector_t.v
    Function: 1101(可重叠)序列检测器测试模块
    Author: Zhang Kaizhou
    Date: 2019-11-6 16:34:22
    ---------------------------------------*/
    `timescale 1ns/1ns
    `define halfperiod 5
    module squence_detector_t(y);
    
    	//定义输出端口
    	output y;
    	
    	//定义内部连线及寄存器
    	reg clk, reset;
    	reg [23 : 0] data; //定义一个24位的寄存器用于存放待测数据码
    	wire d, y;
    	
    	//生成测试信号逻辑
    	initial
    	begin
    		clk = 0; reset = 1;
    		#5 reset = 0;
    		#20 reset = 1; data = 24'b0011_1110_1001_1011_1010_0100;
    		#(`halfperiod * 200) $stop; //执行100个时钟周期
    	end
    	
    	//产生是时钟信号
    	always #`halfperiod clk = ~clk;
    	
    	//用循环移位的方式待测数据码流
    	always@(negedge clk) #5 data = {data[22 : 0], data[23]};
    	assign d = data[23]; //将最高位输入到序列检测器中
    	
    	//实例化
    	squence_detector m0(.clk(clk), .reset(reset), .d(d), .y(y));
    	
    endmodule

**ModelSim仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]  
**总结：**  
由上面的仿真波形可知，1101(可重叠)序列检测器的基本逻辑功能已实现，达到了设计预期。本例重点在于掌握FSM的经典的三段编码风格，这对于复杂状态机的编写十分有利。

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