FPGA 十进制转化为二进制

谁践踏了优雅 2022-12-28 06:17 223阅读 0赞

请原谅： 代码还没有写完，后面一定补上

module operation(
      input  clk ,
      input  rst_n,
      output reg  [3:0]  num_add,
      output reg  [3:0]  num_sub,
      output reg  [6:0]  num_mul, 
      output reg  [3:0]  num_div,
      output reg  [3:0]  num_rem,
      output reg  [9:0]  num_bin 
      );
    reg [3:0] num1;
    reg [3:0] num2;
    reg [9:0] bin_num;
    reg   [3:0] cnt;
    reg  [9:0]  ans;
    // 加减乘除四则运算
    always@(posedge clk or negedge rst_n)begin 
         if(!rst_n)begin 
    	        num1<=4'd8;
    			  num2<=4'd2;
    	  end 
    	  else  begin 
    	        num_add<=num1+num2;
    			  num_sub<=num1-num2;
    			  num_mul<=num1*num2;
    			  num_rem<=num1%num2;
    			  num_div<=num1/num2;
    	  end 
    end 
    // 十进制如何转化为二进制, 二进制的最开始的余数为低位,后面得到的余数为高位,利用拼接的方法
    
    
    always@(posedge clk or negedge rst_n)begin 
       if(!rst_n)begin 
    	   bin_num<=10'b0;
    		cnt<=4'd0;
    		ans<= ;
       end 
    	else begin 
    	   <=
          		
    		
    	end 
    		
    		
            
    end 
    
    
    
    endmodule

验证代码：

`timescale 1ns/1ns
    module operation_tb();
     
    reg clk;
    reg rst_n;
    wire [3:0]  num_add;
    wire [3:0]  num_sub;
    wire [6:0]  num_mul; 
    wire [3:0]  num_div;
    wire [3:0]  num_rem;
    
    parameter T=20;
    initial begin 
          clk=1'b0;
    		rst_n=1'b0;
    		#20        rst_n      = 1'b1;  //在第20ns的时候复位信号信号拉高 
    		#1000   
    		$stop;		
    end 
    always#(T/2) clk<=~clk;
    operation  operation_v1(
      .clk  (clk),
      .rst_n (rst_n),
      .num_add (num_add),
      .num_sub  (num_sub),
      .num_mul   (num_mul), 
      .num_div  (num_div),
      .num_rem  (num_rem)
    );
     
    endmodule