HDB3编译码verilog程序

男娘i 2022-09-04 12:41 132阅读 0赞

/\*module shiftregisterHDB3(clk,reset,Qin,Qoutodd,,Qouteven,nownum;  
input clk,Qin,reset;  
output Qoutodd,Qouteven;  
output \[9:0\] nownum;

reg \[9:0\] nownum;

always @(posedge clk or posedge reset)  
begin  
if(reset)  
nownum<=10'b0000\_0000\_00;  
else  
begin  
nownum<=(nownum>>1);  
nownum\[9\]<=Qin;  
end  
end

assign Qoutodd=nownum\[1\];  
assign

endmodule  
\*/  
/\*  
module shiftresister(clk,reset,load,Qin,Qload,Qout);  
input clk,reset,load,Qin,Qload;  
output Qout;  
reg \[4:0\] num;

always @(posedge clk)  
begin  
temp<=Qin;  
end

always @(posedge reset)  
begin  
num<=5'b0000\_0;  
end

always @(negedge clk)  
begin  
if(!reset)  
begin  
num<=(num>>1);  
num\[4\]<=Qin;  
  
end  
end

assign Qout=num\[0\];  
  
\*/

module HDB3(E1clk,reset,RXD,E1outp,E1outn);  
input E1clk,reset,RXD;  
output E1outp,E1outn;

reg\[4:0\] hdb3p,hdb3n;  
reg E1outp1,E1outn1,fourzero,remB,remV,oddeven,temp;  
reg \[2:0\] count;  
//变量说明:  
//fourzero:在连续输入四个零的情况下为1；  
//remB：当将高电平1编码为B+时,其值为1;当将高电平1编码为B-时,其值为0;  
//remV：当将连续零的第四位编码为V+时,其值为1;当将连续零的第一位编码为V-时,其值为0;  
//oddeven: 当前要编为V码的位与前一个被编为V码的位之间有奇数个B码时为1，偶数个为0;

always @(posedge E1clk)  
//四个连续零检测模块：若当前输入为1，则计数清零；当前输入为零时，开始计数。  
//当计数到四时，即说明已经连续出现了四个零，将fourzero变量置1，作为编码电路的一个信息。  
begin  
temp<=RXD;  
if(!RXD)  
count<=count+3'b001;  
else  
begin  
count<=3'b000;  
// fourzero<=1'b0;  
end  
if(count==3'b011)  
begin  
count<=3'b000;  
fourzero<=1'b1;  
end  
else  
fourzero<=1'b0;  
end

always @(negedge E1clk or posedge reset)  
begin  
if(reset)  
begin  
// E1outp<=0;  
// E1outn<=0;  
// fourzero<=0;  
remB<=1'b0;  
remV<=1'b0;  
oddeven<=1'b0;  
hdb3p<=5'b0000\_0;  
hdb3n<=5'b0000\_0;  
end  
  
else  
begin  
hdb3p<=hdb3p>>1;  
hdb3n<=hdb3n>>1;  
E1outp1<=hdb3p\[0\];  
E1outn1<=hdb3n\[0\];  
/\*begin  
if(!RXD)  
count<=count+1'b1;  
else  
begin  
count<=3'b000;  
// fourzero<=1'b0;  
end  
if(count==3'b011)  
begin  
count<=3'b000;  
fourzero<=1'b1;  
end  
else  
fourzero<=1'b0;  
end\*/  
  
if(temp)  
begin  
if(remB)  
begin  
hdb3p\[4\]<=1'b0;  
hdb3n\[4\]<=1'b1;  
remB<=~remB;  
oddeven<=~oddeven;  
end  
else  
begin  
hdb3n\[4\]<=1'b0;  
hdb3p\[4\]<=1'b1;  
remB<=~remB;  
oddeven<=~oddeven;  
end  
end  
else  
begin  
if(!fourzero)  
begin  
hdb3n\[4\]<=1'b0;  
hdb3p\[4\]<=1'b0;  
end  
else  
begin  
if(!oddeven)  
begin  
if(remB)  
begin  
hdb3n\[1\]<=1'b1;  
hdb3p\[1\]<=1'b0;  
remB<=~remB;  
oddeven<=~oddeven;  
end  
else  
begin  
hdb3p\[1\]<=1'b1;  
hdb3n\[1\]<=1'b0;  
remB<=~remB;  
oddeven<=~oddeven;  
end  
end  
if(remV)  
begin  
hdb3n\[4\]<=1'b1;  
hdb3p\[4\]<=1'b0;  
remV<=~remV;  
oddeven<=1'b0;  
end  
else  
begin  
hdb3p\[4\]<=1'b1;  
hdb3n\[4\]<=1'b0;  
remV<=~remV;  
oddeven<=1'b0;  
end  
end  
end  
end

end  
assign E1outp=E1outp1&(~E1clk);  
assign E1outn=E1outn1&(~E1clk);  
  
/\*  
always @(E1clk)  
begin  
E1outp<=hdb3p\[0\]&(~E1clk);  
E1outn<=hdb3n\[0\]&(~E1clk);  
end \*/  
endmodule