About Cache Coherence, Atomic Operation, Memory Ordering, Memory Barrier, Volatile

矫情吗；* 2022-08-26 12:12 207阅读 0赞

写这篇文章的起因是看到何登成博士发的一个[微博问题][Link 1]，如下：

![Center][]

自己想不太明白，顺下找了他以前分享的一些资料和其他人的博客阅读，在这里做个笔记，内容主要来自何博的ppt。关于微博问题的讨论最后再说。

实际上问题所涉及到的知识点非常多，我也有很多还没理解，这里尽量省去细枝末节，更详细的内容请参考附录链接。

**一. Cache Coherence**

1. What is a cache? cache line ?

cache : Small, fast storage used to improve average access time to slow memory.

cache line : The minimum amount of cache which can be loaded or stored to memory

2. Cache Write Policy

– Write Back

•脏数据，写出到Cache；

– Write Through

•脏数据，写穿到Memory;

– Write Invalidate（大部分系统采用）

Write时，同时发出Invalidate消息，使得所有其他CPU L1/L2 Cache中同一Cache Line失效

– Write Update

•Write时，同时更新其他CPU L1/L2 Cache中同一Cache Line；

3. Cache Coherence

在多核处理器上，由于每个核都有自己的cache，如果有多层cache，如L3往往是多核共享的。所以会存在Cache Coherence 问题，

False cache line sharing：When one processor modifies a value in its cache, other processors cannot use the old value anymore.

That memory location will be invalidated in all of the caches. Furthermore, since caches operate on the granularity of cache lines and

not individual bytes, the entire cache line will be invalidated in all caches!

Cache Coherence Protocol (MESI, MOESI)，作用于CPU Cache与Memory层面，若操作的数据在Register，或者是Register与L1

Cache之间(下面会提到的Store Buffer，Load Buffer)，则这些数据不会参与Cache Coherence协议。

**二、Atomic Operation**

•An operation acting on shared memory is atomic if it completes in a single step relative to other threads. When an atomic store is performed on a shared variable, no other thread can observe the modification half-complete. When an atomic load is performed on a shared variable, it reads the entire value as it appeared at a single moment in time.

1. 高级语言与汇编指令的映射

高级语言(如：C/C++)，被编译为汇编语言，才能够被执行。因此，高级语言与汇编语言之间，存在着几种简单的映射关系。

•Simple Write

– Write to Memory ![Center 1][]

– Atomic

•Simple Read

–Read from Memory ![Center 2][]

–Atomic （ 注：实际上这里是指将a 读取到寄存器eax是atomic的，赋值语句b=a 包括两条汇编命令，不是atomic的）

•Read-Modify-Write(RMW)

– Read from Memory

– Modify ![Center 3][]

– Write to Memory

– Non-Atomic

•Read/Write 64 Bits on 32 Bits Systems

– Write：Non-Atomic

![Center 4][]

– Read：Non-Atomic

2. Non-Atomic 的危害（在32位机上读写64位数如上图）

•Half Write

– mov dword ptr \[c\], 2 执行后，会短暂出现c的half write现象；

•Half Read

–若c 出现half write，则读取c 会出现half read现象；

•Composite Write

– 两个线程同时write c，一个完成，一个half write，则c的值，来自线程1，2两个write操作的组合；

•危害

– 出现Half Read，会导致程序判断逻辑出错；出现Composite Write，会导致数据出错

3. 如何消除Non-Atomic Read/Write？

•Intel/AMD CPU 平台方面 (参考各CPU白皮书)

– Aligned 2-，4-Byte Simple Read/Write -> Atomic

– Aligned 8-Byte，CPU型号判断-> 一般为Atomic

– Unaligned 2-, 4-, 8-Byte，CPU型号判断 -> 尽量少用

•RMW Operation

尽量使用系统自带的，或者是提供的原子操作函数；这些函数，对不同CPU类型，做了较好的封装，更加易用；

– [Windows Synchronization Functions][]

– [Linux Built-in Functions for Atomic Memory Access][]

–  [C++ 11 Atomic Operations Library][C_ 11 Atomic Operations Library]

4. Atomic Instructions and Lock

•Atomic Instructions

– 常见指令：CMPXCHG，XCHG，XADD，...

– CMPXCHG(compare-and-exchange)

![Center 5][]

•将Operand1(Reg/Mem)中的内容与EAX比较，若相等，则拷贝Operand2(Reg)中的内容至Operand1；若不等，

则将Operand2中的数据写入EAX；

•一个Atomic RMW操作，若Operand1为Memory，则CMPXCHG指令还需要Lock指令配合 (Lock prefix)；

•Lock Instruction

![Center 6][]

– Lock指令是一个前缀，可以用在很多指令之前，代表当前指令 所操作的内存(Memory)，在指令执行期间，只能被当前CPU所用；

– Intel’s Description about Lock Instruction

![Center 7][]

– Lock with CMPXCHG

![Center 8][]

\- x++可以用汇编来写 : \_\_asm LOCK inc dword ptr\[x\]

**三、Memory Ordering(Reordering)**

1.Reordering

Reads and writes do not always happen in the order that you have written them in your code.

用户程序，无论是在编译期间，还是在执行期间，都会产生Reordering；

•Why Reordering

– Performance

•Reordering Principle

– In single threaded programs from the programmer's point of view, all operations appear to have been executed in the order specified, with all inconsistencies hidden by hardware.

–- 一段程序，在Reordering前，与Reordering后，拥有相同的执行效果(Single Thread)

2.Reordering type

•Examples

– Example1  
•经过编译优化，A, B 赋值操作被Reorder；出现在编译期间的Reordering，称之为 Compiler Reordering；

![Center 9][] ![Center 10][] ![Center 11][]

![Center 12][] ![Center 13][]

\-- Example 2

load 操作被提前； 出现在执行期间的Reordering，称之为 CPU Memory Reordering；

•假设X，Y初始化为0； 根据p1和p2的运行顺序不同，按常规不乱序执行来说，r1, r2 的值可能为0,1(p1 first); 1,0;(p2 first) 1,1(concurrent); 但一定不会出现0,0;的状态，实际上测试运行多次，会出现0,0;的状态，因为cpu在运行指令时将load 操作提前了。测试代码 [点这][Link 2]。 (where blank lines have been inserted to highlight the apparent order of operations)

![Center 14][] ![Center 15][]

![Center 16][]

3. CPU Memory Ordering/Reordering

The term memory ordering refers to the order in which the processor issues reads(loads) and writes(stores) through the system bus to system memory. (From [Intel System Programming Guide][] 8.2)

– 为什么需要reordering？

•: L1 Latency 4 clks; L2 10 clks; L3 20 clks; Memory 200 clks -> Huge Latency

•: 考虑指令执行时，read与write的优先级；(CPU设计时，重点考虑)

•CPU Memory Reordering Types

–LoadLoad(读读乱序)、LoadStore(读写乱序)、StoreLoad(写读乱序)、StoreStore(写写乱序)

![Center 17][]

•CPU如何实现Memory Reordering？

– Load/Store Buffer；LineFill Buffer/Write Combining Buffer；Invalidate Message Queue；...

4. CPU Memory Models

Memory consistency models describe how threads may interact through shared memory consistently.

There are many types of memory reordering, and not all types of reordering occur equally often. It all depends on processor you’re targeting and/or the tool chain you’re using for development.

•主要的CPU Memory Models

–Programming Order -> Stronger Memory Model

–Sequential Consistency

–Strict Consistency

–Data Dependency Order -> Weaker Memory Model

–...

![Center 18][]

5. Intel X86/64 Memory Model

•In a single-processor system for memory regions defined as write-back cacheable.

– Reads are not reordered with other reads.

– Writes are not reordered with older reads.

– Writes to memory are not reordered with other writes.

– Reads  may be reordered  with  older writes  to  different locations  but not with older writes to the same location .

•In a multiple-processor system

– Individual processors use the same ordering principles as in a single-processor system.

– **Writes by a single processor** are observed **in the same order** by all processors.

– Writes from an individual processor are NOT ordered with respect to the writes from other processors.

– Memory ordering obeys causality (memory ordering respects transitive visibility).

– **Any two stores** are seen in a **consistent order** by processors other than those performing the stores.

•解读

– 普通内存操作，只可能存在StoreLoad Reordering；

– LoadLoad、LoadStore、StoreStore均不可能Reordering；

– 一个Processor的Writes操作，其他Processor看到的顺序是一致的；

– 不同Processors的Writes操作，是没有顺序保证的；

•StoreLoad Reordering Problem

– [Failure of Dekker’s algorithm][Failure of Dekker_s algorithm]

– [Memory Reordering Caught in the Act][]

**四、Memory Barrier**

A memory barrier, is a type of **barrier instruction** which causes a central processing unit ( CPU ) or compiler to enforce an **ordering constraint** on memory operations issued before and after the barrier instruction. This typically means that certain operations are guaranteed to be performed before the barrier, and others after.

1. Compiler Memory Barrier

Compiler Reordering 能够提高程序的运行效率。但有时候 (尤其是针对Parallel Programming)，我们并不想让Compiler将我们的程序进行Reordering。此时，就需要有一种机制，能够告诉Compiler，不要进行Reordering，这个机制，就是Compiler Memory Barrier。

顾名思义，Complier Memory Barrier就是阻止Compiler进行Reordering的Barrier Instruction；

•Compiler Memory Barrier Instructions

– GNU

> •asm volatile(""::: "memory");
> 
> •\_\_asm\_\_ \_\_volatile\_\_ ("" :::"memory");

– Intel ECC Compiler

> •\_\_memory\_barrier();

– Microsoft Visual C++

> •\_ReadWriteBarrier();

•使用Compiler Memory Barrier后，即使-O2 编译优化，也不会乱序。

![Center 19][] ![Center 12][]

•注意：

– Compiler Memory Barrier只是一个通知的标识，告诉Compiler在看到此指令时，不要对此指令的上下部分做Reordering。

– 在编译后的汇编中，Compiler Memory Barrier消失，CPU不能感知到Compiler Memory Barrier的存在，这点与后面提到的CPU Memory Barrier有所不同；

2. Cpu Memory Barrier

顾名思义，Compiler Memory Barrier既然是用来告诉Compiler在编译阶段不要进行指令乱排，那么CPU Memory Barrier就是用来告诉CPU，在执行阶段不要交互两条操作内存的指令的顺序；

注意：由于CPU在执行时，必须感知到CPU Memory Barrier的存在，因此 **CPU Memory Barrier是一条真正的指令**，存在于编译后的汇编代码中；

（1）、4种基本的CPU Memory Barriers

– LoadLoad Barrier

– LoadStore Barrier

– StoreLoad Barrier

– StoreStore Barrier

（2）、更为复杂的CPU Memory Barriers

– **Store Barrier (Write Barrier)**

•所有在Store Barrier前的Store操作，必须在Store Barrier指令前执行完毕；而所有Store Barrier指令后的Store操作，必须在Store指令执行结束后才能开始；

•Store Barrier只针对Store(Write)操作，对Load无任何影响；

– **Load Barrier (Read Barrier)**

•将Store Barrier的功能，全部换为针对Load操作即可；

**–Full Barrier**

•Load+ Store Barrier，Full Barrier两边的任何操作，均不可交换顺序；

（3）、Memory Barrier Instructions in CPU

•x86, x86-64, amd64

– lfence： Load Barrier

– sfence： Store Barrier

– mfence： Full Barrier

•PowerPC

– sync： Full Barrier

•MIPS

– sync： Full Barrier

•Itanium

– mf： Full Barrier

•ARMv7

– dmb

– dsb

– isb

3.Use CPU Memory Barrier Instructions(x86)

•Only CPU Memory Barrier

– asm volatile(“mfence”);

•CPU + Compiler Memory Barrier

– asm volatile(“mfence” ::: ”memory”);

•Use Memory Barrier in C/C++

![Center 20][]

![Center 21][]

4. Use Lock Instruction to Implement a Memory Barrier

Reads or writes cannot be reordered with I/O instructions, **locked instructions**, or serializing instructions.

既然read/write不能穿越locked instructions进行reordering，那么所有带有lock prefix的指令，都构成了一个天然的Full Memory Barrier；

•lock addl

– asm volatile("lock; addl $0,0(%%esp)" ::: "memory")

addl $0,0(%%esp) -> do nothing

lock; -> to be a cpu memory barrier

“memory” -> to be a compiler memory barrier

•xchg

– asm volatile(“xchgl (%0),%0” ::: “memory”)

Question: why xchg don’t need lock prefix?

Answer: The LOCK prefix is automatically assumed for XCHG instruction.

•lock cmpxchg

5.Memory Barriers in Compiler & OS

•Linux(x86,x86-64)

– smp\_rmb()

– smp\_wmb()

– smp\_mb()

![Center 22][] ![Center 23][]

•Windows(x86,x86-64)

– MemoryBarrier()

![Center 24][]

6. X86 Memory Ordering with Memory Barrier

•In a single-processor system for memory regions defined as write-back cacheable.

– 注：新增部分

– Reads or writes cannot be reordered with I/O instructions, **locked instructions**, or serializing instructions.

– **Reads** cannot pass earlier **LFENCE** and  **MFENCE** instructions.

– **Writes** cannot pass earlier LFENCE, SFENCE, and MFENCE instructions.

– LFENCE instructions cannot pass earlier reads.

– SFENCE instructions cannot pass earlier writes.

– MFENCE instructions cannot pass earlier reads or writes.

•In a multiple-processor system

– 注：新增部分

–  **Locked instructions have a total order**.

**五、Read Acquire vs Write Release**

1.Read Acquire and Write Release ![Center 25][]

–Two Special Memory Barriers. ![Center 26][]

– Definition

•A read-acquire executes before all reads and writes by the same thread that follow it in program order.

•A write-release executes after all reads and writes by the same thread that precede it in program order.

2.Read Acquire and Write Release 的作用

![Center 27][] ![Center 28][]

•Read Acquire and Write Release Barriers

– Read Acquire

•LoadLoad + LoadStore Barrier

– Write Release

•LoadStore + StoreStore Barrier

•解读

– Read Acquire + Write Release语义，是所有锁实现的基础(Spinlock, Mutex, RWLock, ...)，所有被\[Read Acquire, Write Release\]包含的区域，即构成了一个临界区，临界区内的指令，确保不会在临界区外运行。因此，Read Acquire又称为 Lock Acquire，Write Release又称为 Unlock Release；

3.How to Implement Read Acquire/Write Release?

•Intel X86, X86-64

– Full Memory Barrier

•mfence

•locked instruction

•Compiler and OS

– Linux

•smp\_mb()

– Windows

•Functions with Acquire/Release Semantics

•InterlockedIncrementAcquire ()...

4. Extension：StoreLoad Reorder

•Question

–为什么Intel CPU在LoadLoad，LoadStore，StoreLoad，StoreStore乱序中，仅仅保持了StoreLoad乱序？

–为什么LoadLoad/LoadStore/StoreStore Barrier 乱序被称之为 lightweight Barrier? 而StoreLoad Barrier 则为 Expensive Barrier？

•on PowerPC, the lwsync (short for “lightweight sync”)instruction acts as all three \#LoadLoad, \#LoadStore and \#StoreStore barriers

at the same time, yet is less expensive than the sync instruction,which includes a \#StoreLoad barrier.

•Answer

– Store Buffer;

– Store异步不影响指令执行；

– Load只能同步；

•注意

– Intel CPU，Load自带Acquire Semantics；Store自带Release Semantics；

**六、Volatile：C/C++ vs Java**

•Volatile

– 易失的，不稳定的...

•Volatile in C/C++

The volatile keyword is used on variables that may be modified simultaneously by other threads. This warns the compiler to fetch them fresh each time, rather than caching them in registers. (r**ead/write actually happens**)

– No reordering occurs between different volatile reads/writes. (**only volatile variables guarantee no reordering**)

• Volatile in Java

– (The Same as C/C++)，Plus

– Volatile reads and writes establish a [happens-before relationship][], much like acquiring and releasing a mutex. (no reordering takes place)

• Read Volatile：Acquire Semantics；Write Volatile：Release Semantics；

– Writes and reads of volatile long and double values are always atomic.

• [The Java Language Specification Java SE 7 Edition][]：Chapter 17.7

•Examples

– int answer = 0;

– bool volatile ready;

![Center 29][]

•Question

– Thread2 的answer 会输出什么结果？

– C/C++

• answer= 42 or 0，均有可能；

– Java

• answer= 42，只有唯一的结果；

–Why？

•Java’s Volatile：Write Release Semantics -> ready(true)一定在answer(42)之后执行；

上述讨论表明：C/C++ Volatile变量，与非Volatile变量之间的操作，是可能被编译器优化交换顺序的。但即使把answer也设置为volatile，虽然能够避免被编译器优化而reorer，但不能确保在不同平台cpu上会不会产生指令执行的乱序，所以一定要小心使用，如下所述。

**• C/C++ and "volatile"**

When writing single-threaded code, declaring a variable “volatile” can be very useful. The compiler will not omit or reorder accesses to volatile locations. Combine that with the sequential consistency provided by the hardware, and you’re guaranteed that the loads and stores will appear to happen in the expected order.

However, **accesses to volatile storage may be reordered with non-volatile accesses**, so you have to be careful in multi-threaded uniprocessor environments (explicit compiler reorder barriers may be required). There are no atomicity guarantees, and no memory barrier provisions, so “volatile” doesn’t help you at all in multi-threaded SMP environments. The C and C++ language standards are being updated to address this with built-in atomic operations.

If you think you need to declare something “volatile”, that is a strong indicator that you should be using one of the atomic operations instead.

**七、微博问题讨论**

测试代码如下：

C++ Code

<table style="width:100%; font-family:'Consolas','Courier New'; font-size:12px; vertical-align:text-top; line-height:15px"> 
 <tbody> 
 <tr> 
 <td style="color:#008284; background-color:#e3e3e3; vertical-align:text-top"> 
 <div style="margin:7px; text-align:right; white-space:nowrap">
 1 
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 67 
 68 
 
 </div> </td> 
 <td style="background-color:#008284; padding:1px"> 
 <div style="border:1px #008284 solid"></div> </td> 
 <td style="background-color:rgb(239,239,239); width:100%; vertical-align:text-top"> 
 <div style="margin:7px"> 
 //&nbsp;g++&nbsp;-o&nbsp;reorder&nbsp;-O3&nbsp;reorder.c&nbsp;-lpthread //&nbsp;Run&nbsp;in&nbsp;X86&nbsp;CPU&nbsp;(Intel/AMD) 
 
 #include&nbsp;&lt;stdio.h&gt; 
 
 #include&nbsp;&lt;stdlib.h&gt; 
 
 #include&nbsp;&lt;pthread.h&gt; 
 
 #include&nbsp;&lt;semaphore.h&gt; 
 
 
 #define&nbsp;N&nbsp; 
 100000 
 
 
 sem_t&nbsp;sem_ac,&nbsp;sem_bc,&nbsp;sem_fin; 
 
 
 static&nbsp; 
 volatile&nbsp; 
 int&nbsp;A; 
 
 static&nbsp; 
 volatile&nbsp; 
 int&nbsp;B; 
 
 static&nbsp; 
 volatile&nbsp; 
 int&nbsp;C; 
 
 
 void&nbsp;*setAC( 
 void&nbsp;*args) 
 { 
 &nbsp;&nbsp;&nbsp;&nbsp; 
 for&nbsp;(;;) 
 &nbsp;&nbsp;&nbsp;&nbsp;{ 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_wait(&amp;sem_ac); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A&nbsp;=&nbsp; 
 1; 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;__sync_synchronize(); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;C&nbsp;=&nbsp;B; 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_post(&amp;sem_fin); 
 &nbsp;&nbsp;&nbsp;&nbsp;} 
 } 
 
 
 void&nbsp;*setBC( 
 void&nbsp;*args) 
 { 
 &nbsp;&nbsp;&nbsp;&nbsp; 
 for&nbsp;(;;) 
 &nbsp;&nbsp;&nbsp;&nbsp;{ 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_wait(&amp;sem_bc); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;B&nbsp;=&nbsp; 
 1; 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;__sync_synchronize(); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;C&nbsp;=&nbsp;A; 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_post(&amp;sem_fin); 
 &nbsp;&nbsp;&nbsp;&nbsp;} 
 } 
 
 
 int&nbsp;main( 
 int&nbsp;argc,&nbsp; 
 char&nbsp;*argv[]) 
 { 
 &nbsp;&nbsp;&nbsp;&nbsp;pthread_t&nbsp;t1,&nbsp;t2; 
 &nbsp;&nbsp;&nbsp;&nbsp; 
 int&nbsp;got&nbsp;=&nbsp; 
 0,&nbsp;iters&nbsp;=&nbsp; 
 0; 
 
 &nbsp;&nbsp;&nbsp;&nbsp;sem_init(&amp;sem_ac,&nbsp; 
 0,&nbsp; 
 0); 
 &nbsp;&nbsp;&nbsp;&nbsp;sem_init(&amp;sem_bc,&nbsp; 
 0,&nbsp; 
 0); 
 &nbsp;&nbsp;&nbsp;&nbsp;sem_init(&amp;sem_fin,&nbsp; 
 0,&nbsp; 
 0); 
 
 &nbsp;&nbsp;&nbsp;&nbsp;pthread_create(&amp;t1,&nbsp; 
 NULL,&nbsp;setAC,&nbsp; 
 NULL); 
 &nbsp;&nbsp;&nbsp;&nbsp;pthread_create(&amp;t2,&nbsp; 
 NULL,&nbsp;setBC,&nbsp; 
 NULL); 
 
 &nbsp;&nbsp;&nbsp;&nbsp; 
 for&nbsp;(;;&nbsp;iters++) 
 &nbsp;&nbsp;&nbsp;&nbsp;{ 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A&nbsp;=&nbsp;B&nbsp;=&nbsp;C&nbsp;=&nbsp; 
 0; 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_post(&amp;sem_ac); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_post(&amp;sem_bc); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_wait(&amp;sem_fin); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sem_wait(&amp;sem_fin); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
 if&nbsp;(C&nbsp;==&nbsp; 
 0) 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;{ 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;printf( 
 "got&nbsp;%d&nbsp;reorders&nbsp;after&nbsp;%d&nbsp;iterations\n",&nbsp;++got,&nbsp;iters); 
 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;} 
 &nbsp;&nbsp;&nbsp;&nbsp;} 
 
 &nbsp;&nbsp;&nbsp;&nbsp; 
 return&nbsp; 
 0; 
 } 
 </div> </td> 
 </tr> 
 </tbody> 
</table>

注：\_\_sync\_synchronize() 是gcc 提供的一个 full memory barrier.

在多核处理器上不管加不加内存屏障都可能会输出C==0的情况。

如果不加，有两个原因，一个是指令执行乱序如（A=1 与 C=B 交换），另一个是线程调度在多个核上跑的时候。每个核心的寄存器都是独立的，而C=B 是两条汇编指令，出现 c==0 的情况跟下面单核类似，不赘述。

如果加了，就只剩下线程跑在多核上的影响了。

在单核处理器上（或者通过绑定到一个核上运行），即使加了内存屏障还是可以输出c=0的情况，虽然概率小很多。

ASM Code

假设先运行线程1一直到mov 0x804a038,%eax 完，此时线程1的eax为0，然后切换到线程2运行一直到一个循环结束，此时c=1，接着切换回线程1

运行 mov %eax,0x804a034， c又被覆盖成0了。但在这么短的时间内一般不会发生context switching，所以c==0 出现的概率很小。

附录链接：

CPU cache and memory ordering.pptx http://vdisk.weibo.com/s/JFrnp

SMP primer for android [http://developer.android.com/training/articles/smp.html][http_developer.android.com_training_articles_smp.html]

C/C++ Volatile关键词深度剖析 http://hedengcheng.com/?p=725

并发编程系列之一：锁的意义 http://hedengcheng.com/?p=803

多线程程序中操作的原子性 [http://www.parallellabs.com/2010/04/15/atomic-operation-in-multithreaded-application/][http_www.parallellabs.com_2010_04_15_atomic-operation-in-multithreaded-application]

[Gallery of Processor Cache Effects][]http://igoro.com/archive/gallery-of-processor-cache-effects/

[Link 1]: http://weibo.com/2216172320/ADZVUhxb4
[Center]: /images/20220824/3fe11519153049ee93879bbd77dc8d0d.png
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[Center 4]: /images/20220824/5366c9b80f49411d8948a9006cc12d51.png
[Windows Synchronization Functions]: http://msdn.microsoft.com/en-us/library/ms686360%28v=vs.85%29.aspx
[Linux Built-in Functions for Atomic Memory Access]: http://gcc.gnu.org/onlinedocs/gcc-4.4.3/gcc/Atomic-Builtins.html
[C_ 11 Atomic Operations Library]: http://en.cppreference.com/w/cpp/atomic
[Center 5]: /images/20220824/96a31a5314c5499ca11d9cdc00e43e91.png
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[Center 9]: https://img-blog.csdn.net/20140405162549031?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvam51X3NpbWJh/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/Center
[Center 10]: https://img-blog.csdn.net/20140405162841250?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvam51X3NpbWJh/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/Center
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[Link 2]: http://vdisk.weibo.com/s/I6KmT
[Center 14]: https://img-blog.csdn.net/20140405163034125?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvam51X3NpbWJh/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/Center
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[Intel System Programming Guide]: http://download.intel.com/products/processor/manual/253668.pdf
[Center 17]: /images/20220824/83a4e1a11c79469389606e564b6e1561.png
[Center 18]: /images/20220824/fc3013678eae476b86c8dab1640a5774.png
[Failure of Dekker_s algorithm]: http://bartoszmilewski.com/2008/11/05/who-ordered-memory-fences-on-an-x86/
[Memory Reordering Caught in the Act]: http://preshing.com/20120515/memory-reordering-caught-in-the-act/
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[Center 28]: /images/20220824/7d69335dc9d1405d9bc4391da445eba7.png
[happens-before relationship]: http://en.wikipedia.org/wiki/Happened-before
[The Java Language Specification Java SE 7 Edition]: http://docs.oracle.com/javase/specs/jls/se7/jls7.pdf
[Center 29]: /images/20220824/6de085caa9dd4f8b85e4af6f4a08b805.png
[http_developer.android.com_training_articles_smp.html]: http://developer.android.com/training/articles/smp.html
[http_www.parallellabs.com_2010_04_15_atomic-operation-in-multithreaded-application]: http://www.parallellabs.com/2010/04/15/atomic-operation-in-multithreaded-application/
[Gallery of Processor Cache Effects]: http://igoro.com/archive/gallery-of-processor-cache-effects/