ARM 指令 CORTEX-M0

系统管理员 2022-07-12 04:09 261阅读 0赞

http://blog.csdn.net/qq1987924/article/details/35316955

处理器使用的是ARMv6-M Thumb指令集，包括大量的32位的使用Thumb-2技术的指令。表7-22列出了Cortex-M0指令和它们的周期数。周期计数以零等待状态的系统为基准。

表7-22 Cortex-M0指令和它们的周期数

续表

<table> 
 <tbody> 
 <tr> 
 <td> 操作 </td> 
 <td> 描述 </td> 
 <td> 汇编指令 </td> 
 <td> 周期 </td> 
 </tr> 
 <tr> 
 <td> Any to Any </td> 
 <td> ADD Rd,Rd,Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Any to PC </td> 
 <td> ADD PC,PC,Rm </td> 
 <td> 3 </td> 
 </tr> 
 <tr> 
 <td> 8-bit immediate </td> 
 <td> ADDS Rd,Rd,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> With carry </td> 
 <td> ADCS Rd,Rd,Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Immediate to SP </td> 
 <td> ADD SP,SP,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Form address from SP </td> 
 <td> ADD Rd,SP ,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Form address from PC </td> 
 <td> ADR Rd,&lt;label&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Subtract </td> 
 <td> Lo to Lo </td> 
 <td> SUBS Rd,Rn,Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> 3-bit immediate </td> 
 <td> SUBS Rd,Rn,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> 8-bit immediate </td> 
 <td> SUBS Rd,Rd,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> With carry </td> 
 <td> SBCS Rd,Rd,Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Immediate from SP </td> 
 <td> SUB SP,SP,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Negate </td> 
 <td> RSBS Rd,Rn,#0 </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow"></a><a style="color:rgb(51,102,153)" rel="nofollow"></a>Multiply </td> 
 <td> Multiply </td> 
 <td> MULS Rd,Rm,Rd </td> 
 <td> 1或32 </td> 
 </tr> 
 <tr> 
 <td> Compare </td> 
 <td> Compare </td> 
 <td> CMP Rn,Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Negative </td> 
 <td> CMP Rn,Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Immediate </td> 
 <td> CMP Rn,#&lt;imm&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Logical </td> 
 <td> AND </td> 
 <td> ANDS Rd, Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Exclusive OR </td> 
 <td> EORS Rd, Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> OR </td> 
 <td> ORRS Rd, Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Bit clear </td> 
 <td> BICS Rd, Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Move NOT </td> 
 <td> MVNS Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> AND test </td> 
 <td> TST Rn, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow">Shift</a> </td> 
 <td> Logical shift left by immediate </td> 
 <td> LSLS Rd, Rm, #&lt;shift&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Logical shift left by register </td> 
 <td> LSLS Rd, Rd, Rs </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Logical shift right by immediate </td> 
 <td> LSRS Rd, Rm, #&lt;shift&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Logical shift right by register </td> 
 <td> LSRS Rd, Rd, Rs </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Arithmetic shift right </td> 
 <td> ASRS Rd, Rm, #&lt;shift&gt; </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Arithmetic shift right by register </td> 
 <td> ASRS Rd, Rd, Rs </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Rotate </td> 
 <td> Rotate right by register </td> 
 <td> RORS Rd, Rd, Rs </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Load </td> 
 <td> Word, immediate offset </td> 
 <td> LDR Rd, [Rn, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Halfword, immediate offset </td> 
 <td> LDRH Rd, [Rn, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Byte, immediate offset </td> 
 <td> LDRB Rd, [Rn, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Word, register offset </td> 
 <td> LDR Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 </tbody> 
</table>

续表

<table> 
 <tbody> 
 <tr> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow"></a>操作 </td> 
 <td> 描述 </td> 
 <td> 汇编指令 </td> 
 <td> 周期 </td> 
 </tr> 
 <tr> 
 <td> Halfword, register offset </td> 
 <td> LDRH Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Signed halfword, register offset </td> 
 <td> LDRSH Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Byte, register offset </td> 
 <td> LDRB Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Signed byte, register offset </td> 
 <td> LDRSB Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> PC-relative </td> 
 <td> LDR Rd, &lt;label&gt; </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> SP-relative </td> 
 <td> LDR Rd, [SP, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Multiple, excluding base </td> 
 <td> LDM Rn!, {&lt;loreglist&gt;} </td> 
 <td> 1+N </td> 
 </tr> 
 <tr> 
 <td> Multiple, including base </td> 
 <td> LDM Rn, {&lt;loreglist&gt;} </td> 
 <td> 1+N </td> 
 </tr> 
 <tr> 
 <td> Store </td> 
 <td> Word, immediate offset </td> 
 <td> STR Rd, [Rn, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Halfword, immediate offset </td> 
 <td> STRH Rd, [Rn, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Byte, immediate offset </td> 
 <td> STRB Rd, [Rn, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Word, register offset </td> 
 <td> STR Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Halfword, register offset </td> 
 <td> STRH Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Byte, register offset </td> 
 <td> STRB Rd, [Rn, Rm] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> SP-relative </td> 
 <td> STR Rd, [SP, #&lt;imm&gt;] </td> 
 <td> 2 </td> 
 </tr> 
 <tr> 
 <td> Multiple </td> 
 <td> STM Rn!, {&lt;loreglist&gt;} </td> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow"></a><a style="color:rgb(51,102,153)" rel="nofollow"></a>1+N </td> 
 </tr> 
 <tr> 
 <td> Push </td> 
 <td> Push </td> 
 <td> PUSH {&lt;loreglist&gt;} </td> 
 <td> 1+N </td> 
 </tr> 
 <tr> 
 <td> Push with link register </td> 
 <td> PUSH {&lt;loreglist&gt;, LR} </td> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow"></a><a style="color:rgb(51,102,153)" rel="nofollow"></a>1+N </td> 
 </tr> 
 <tr> 
 <td> Pop </td> 
 <td> Pop </td> 
 <td> POP {&lt;loreglist&gt;} </td> 
 <td> 1+N </td> 
 </tr> 
 <tr> 
 <td> Pop and return </td> 
 <td> POP {&lt;loreglist&gt;, PC} </td> 
 <td> 4+N </td> 
 </tr> 
 <tr> 
 <td> Branch </td> 
 <td> Conditional </td> 
 <td> B&lt;cc&gt; &lt;label&gt; </td> 
 <td> 1或3 </td> 
 </tr> 
 <tr> 
 <td> Unconditional </td> 
 <td> B&lt;label&gt; </td> 
 <td> 3 </td> 
 </tr> 
 <tr> 
 <td> With link </td> 
 <td> BL&lt;label&gt; </td> 
 <td> 4 </td> 
 </tr> 
 <tr> 
 <td> With exchange </td> 
 <td> BX Rm </td> 
 <td> 3 </td> 
 </tr> 
 <tr> 
 <td> With link and exchange </td> 
 <td> BLX Rm </td> 
 <td> 3 </td> 
 </tr> 
 <tr> 
 <td> Extend </td> 
 <td> Signed halfword to word </td> 
 <td> SXTH Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Signed byte to word </td> 
 <td> SXTB Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Unsigned halfword </td> 
 <td> UXTH Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Unsigned byte </td> 
 <td> UXTB Rd, Rm </td> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow"></a><a style="color:rgb(51,102,153)" rel="nofollow"></a>1 </td> 
 </tr> 
 <tr> 
 <td> Reverse </td> 
 <td> Bytes in word </td> 
 <td> REV Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Bytes in both halfwords </td> 
 <td> REV16 Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> Signed bottom half word </td> 
 <td> REVSH Rd, Rm </td> 
 <td> 1 </td> 
 </tr> 
 <tr> 
 <td> State change </td> 
 <td> Supervisor Call </td> 
 <td> SVC #&lt;imm&gt; </td> 
 <td> - </td> 
 </tr> 
 <tr> 
 <td> Disable interrupts </td> 
 <td> CPSID i </td> 
 <td> 1 </td> 
 </tr> 
 </tbody> 
</table>

ISO/IEC的C代码不能直接地获取一些Cortex-M0的指令。表7-23列举了CMSIS的C编译器中提供的部分内部函数用于产生这些指令。如果一个C编译器不支持恰当的内部函数，则需要用内嵌汇编来获取有关指令。

表7-23 CMSIS内部函数

<table> 
 <tbody> 
 <tr> 
 <td> 指令 </td> 
 <td> CMSIS内部函数 </td> 
 <td> 指令 </td> 
 <td> CMSIS内部函数 </td> 
 </tr> 
 <tr> 
 <td> CPSIE i </td> 
 <td> void __enable_irq(void) </td> 
 <td> REV </td> 
 <td> <a style="color:rgb(51,102,153)" rel="nofollow"></a><a style="color:rgb(51,102,153)" rel="nofollow"></a>uint32_t __REV(uint32_t int value) </td> 
 </tr> 
 <tr> 
 <td> CPSID i </td> 
 <td> void __disable_irq(void) </td> 
 <td> REV16 </td> 
 <td> uint32_t __REV16(uint32_t int value) </td> 
 </tr> 
 <tr> 
 <td> ISB </td> 
 <td> void __ISB(void) </td> 
 <td> REVSH </td> 
 <td> uint32_t __REVSH(uint32_t int value) </td> 
 </tr> 
 <tr> 
 <td> DSB </td> 
 <td> void __DSB(void) </td> 
 <td> SEV </td> 
 <td> void __SEV(void) </td> 
 </tr> 
 <tr> 
 <td> DMB </td> 
 <td> void __DMB(void) </td> 
 <td> WFE </td> 
 <td> void __WFE(void) </td> 
 </tr> 
 <tr> 
 <td> NOP </td> 
 <td> void __NOP(void) </td> 
 <td> WFI </td> 
 <td> void __WFI(void) </td> 
 </tr> 
 </tbody> 
</table>

CMSIS也提供了几个函数用于获取特殊的寄存器，如表7-24所示。

表7-24 CMSIS提供的用于获取特殊寄存器的函数

<table> 
 <tbody> 
 <tr> 
 <td> 特殊寄存器 </td> 
 <td> 获取方式 </td> 
 <td> CMSIS函数 </td> 
 </tr> 
 <tr> 
 <td> PRIMASK </td> 
 <td> 读 </td> 
 <td> uint32_t __get_PRIMASK(void) </td> 
 </tr> 
 <tr> 
 <td> 写 </td> 
 <td> void __set_PRIMASK(void) </td> 
 </tr> 
 <tr> 
 <td> CONTROL </td> 
 <td> 读 </td> 
 <td> Uint32_t __get_CONTROL(uint32_t value) </td> 
 </tr> 
 <tr> 
 <td> 写 </td> 
 <td> Void __set_CONTROL(uint32_t value) </td> 
 </tr> 
 <tr> 
 <td> MSP </td> 
 <td> 读 </td> 
 <td> Uint32_t __get_MSP(void) </td> 
 </tr> 
 <tr> 
 <td> 写 </td> 
 <td> Void __set_MSP(uint32_t TopOfMainStack) </td> 
 </tr> 
 <tr> 
 <td> PSP </td> 
 <td> 读 </td> 
 <td> Uint32_t __get_PSP(void) </td> 
 </tr> 
 <tr> 
 <td> 写 </td> 
 <td> Void __set_PSP(uint32_t TopOfMainStack) </td> 
 </tr> 
 </tbody> 
</table>

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