vivado常见compile和elaborate错误

た入场券 2022-05-17 09:59 909阅读 0赞

## complie error类 ##

### 在错误的位置赋值或assign ###

module mod(
        );
        wire w;
        reg r;
        assign w = 1;             // 正确,在initial或always之assign
        r = 0;                    // 错误，在initial或always之外赋值
        assign r = 0;             // 错误，在initial或always之外赋值
        initial begin
            assign w = 0;         // 错误，在initial或always之内assign
            r = 1;                // 正确，在initial或always之内赋值
            assign r = 0;         // 正确，在initial或always之内赋值
        end
    endmodule

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> \[USF-XSim 62\] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED\_8light/LED\_8light.sim/sim\_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

### 使用了未定义的变量 ###

> \[USF-XSim-62\] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED\_8light/LED\_8light.sim/sim\_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

### 在always块中声明变量 ###

always @(count or reset) begin
        reg [7:0] Y;
    end

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### 重复声明变量 ###

reg [7:0] Y;
    wire Y;

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### 语法错误 ###

*    
    
 *  参数间没有加逗号
 *  参数最后加了分号
 *  参数前面没加input或output
 *  参数个数不匹配

### 在错误的地方使用inut/output ###

module multiplier_sim();
        input reg[31:0] multiplicand;
        input reg[31:0] multiplier;
        input wire[31:0] product;
        // 错误：input/output不能定义在模块参数列表之外
    endmodule

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### 在input中使用reg ###

module ALU(
        input reg y
        );
    endmodule

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> \[USF-XSim-62\] ‘compile’ step failed with error(s) while executing ‘D:/vivado/SinglePeriodCPU/SinglePeriodCPU.sim/sim\_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

## elaborate error类 ##

### 参数名字不符 ###

module clock_div(
        input clk,
        output reg clk_div = 0
        );
        // 函数定义
    endmodule
    
    // 错误调用
    clock_div U1(
        .clock(clock), // 参数名应为clk，而不是clock
        .clk_div(clk_sys)
    );

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> \[USF-XSim-62\] ‘elaborate’ step failed with error(s). Please check the Tcl console output or ‘D:/vivado/LED\_8light/LED\_8light.sim/sim\_1/behav/elaborate.log’ file for more information.

### 匿名的组件调用 ###

// 禁止匿名调用，应该为
    // clock_div U1 (
    clock_div ( 
        .clk(clock),
        .clk_div(clk_sys)
    );

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> \[USF-XSim-62\] ‘elaborate’ step failed with error(s). Please check the Tcl console output or ‘D:/vivado/LED\_8light/LED\_8light.sim/sim\_1/behav/elaborate.log’ file for more information.  
> \[VRFC 10-1047\] module instantiation should have an instance name \[“D:/vivado/SinglePeriodCPU/SinglePeriodCPU.srcs/sources\_1/new/CPU.v”:95\]

### 传入reg变量给reg参数 ###

// 模块
    module led_8lights(
        input clock,
        input reset,
        output reg [7:0] Y
        );
        // 模块内容
    endmodule
    
    // 调用
    reg [7:0] Y;  // 错误
    wire [7:0] Y; // 正确
    led_8lights uut(
        .clock(clock),
        .reset(reset),
        .Y(Y)
    );

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> \[VRFC 10-529\] concurrent assignment to a non-net Y is not permitted \[“D:/vivado/LED\_8light/LED\_8light.srcs/sim\_1/new/led\_sim.v”:56\]