Modelsim-altera 仿真顶层原理图的解决办法

忘是亡心i 2022-01-09 07:51 484阅读 0赞

解决办法：  
首先需要将.bdf原理图文件转换为Verilog HDL等第三方EDA工具所支持的标准描述文件。在Quartus下，保持\*.bdf为活动窗口状态，运行\[File\]/\[Create/Update\]/\[Create HDL Design File for Current File\]命令，在弹出窗口选择文件类型为Verilog HDL，即可输出\*.v顶层文件。

下面从：http://www.wlu.ca/science/physcomp/nznotinas/altera\_reference/Quartus\_ModelSim\_schematic.shtml 查询的一个具体的解决办法：

# Quartus II and ModelSim-Altera - using schematic design #

##### Manually Forcing Inputs in ModelSim-Altera #####

**Reference:** [Quartus® II Introduction Using Schematic Designs][Quartus_ II Introduction Using Schematic Designs] \[pdf, 41pp, 2012\]  
**Note:** I strongly recommend that every Quartus project have its own directory.

On your home system, installing Quartus II Web Edition will also install ModelSim®-Altera® Starter Edition .

1.  1.  Use **schematic entry** to enter the logic diagram.
        
         *  Use *File | New Project Wizard* to set up the working directory, project name, top level design entity (should be same as project name) and select a device to program (select any MAX7000S or Cyclone or Cyclone II device).
         *  Use *File | New* to open a new file. From the *Device Design Files* window select *Block Diagram/Schematic File*. Remember to use *File* | *Save As* to rename the project from Block1.bdf (default name) to the project name.
         *  Use symbols from the *primitives* library. After drawing your schematic, remember to add input and output symbols and assign names to the pins.  
              
            
    2.  **Compile** the circuit for a functional simulation by selecting *Processing | Start* | *Start Analysis & Elaboration* from the menu. Fix any errors.  
          
        
    3.  \[Optional\] You can see the minimized circuit structure by selecting *Tools* | *Netlist Viewers* | *RTL Viewer*.  
          
        
    4.  To configure Quartus II (the design and programming package) to work with ModelSim-Altera (the simulation package):

*  **Configure Quartus II to work with ModelSim-Altera** in native link mode:
    
     *  NOTE: this step is DONE ONCE (persistent).
        
         *  On the *Tools* menu, click *Options*. The Options dialog box appears.
         *  In the *Category* list, select *EDA Tool Options*.
         *  For *ModelSim-Altera*, type the path or browse to the directory containing ModelSim-Altera. The directory should be located under the Altera directory, e.g. C:/altera/12.0/modelsim\_ase/win32aloem
         *  Select *OK*.  
              
            
 *  **Configure NativeLink settings**:
    
     *  NOTE: This is DONE ONCE PER PROJECT and the information is stored with the project information.
    
     *  Select *Assignments* | *Settings*. The Settings dialog box appears.
     *  In the Category list, select *EDA Tool Settings* | *Simulation* . The Simulation page appears.
     *  In the Tool name list, select *ModelSim-Altera*. \[Do not turn on Run gate-level simulation automatically after compilation.\]
     *  Format for output netlist should default to *VHDL* and the output directory to *simulation/modelsim*. \[Select/enter if necessary.\]
     *  Select *More EDA Netlist Writer Settings* and change the following options:
        
         *  Turn ON *Generate netlist for functional simulation only*.
         *  Select *OK*.
 *  **Convert the schematic diagram into VHDL code for simulation.**
    
     *  ModelSim requires that the system be specified in an HDL (Hardware Definition Language); we will be using VHDL
     *  Have the schematic open and then select *File* | *Create/Update* | *Create HDL Design File from Current File*.
     *  In the pop-up window, select file type as *VHDL* and the file name will show the name and path of the file. The VHDL file and the BDF file have the same name but different extensions (for example, if your BDF file is example.bdf, the VHDL file created is example.vhd).  
          
        
 *  **Add the VHDL file to the project and compile for simulation**.
    
     *  Open the VHDL file using *File* | *Open*. Then add it to the project using *Project* | *Add Current File to Project*.
        
         *  Note: The VHDL file has three parts:
            
            1.  the library definitions including *work* where your project will be stored,
            2.  the entity definition which is a wrapper that defines the inputs and outputs to the design component, and
            3.  the architecture which defines what your component does.
     *  Remove the BDF file from the project (system can't handle two source files for the same circuit) by selecting *Project* | *Add/Remove Files in Project* and then selecting the BDF file and *Remove*. Note that this does not delete the file (and we do not want to delete the file).
     *  Compile the circuit for a functional simulation by selecting *Processing | Start* | *Start Analysis & Elaboration.*  
          
        
 *  **Launch the ModelSim simulator**.
    
     *  Select *Tools* | *Run EDA Simulation Tool* | *EDA RTL Simulation*. ModelSim will display splash screen. ModelSim will load libraries and compile the project. The transcript pane at the bottom of the screen indicates the scripts that have been run (or are running).
     *  Select *Simulate* | *Start Simulation* to put ModelSim in simulator mode. The Start Simulation Window opens.
     *  The Start Simulation window contains many tabs. The Design tab lists the designs available for simulation; most are system libraries. At the top of list will be *work* (default name for the library containing your program), expand work by selecting the '+'. All components in your design will be listed, select the component (or the top component in a hierarchical design). If appropriate, turn off optimization. Select *OK*.
     *  Then the left hand side of the screen should now contain a *sim* tab that displays the design units in your circuit and the supporting libraries. When a design unit is selected in the *sim* tab, the corresponding signals are shown in the *objects* window on the right hand side of the screen. Signals that are preceded with a plus (+) sign indicate a bus (a group of wires with common function).  
          
        
 *  **Open waveform window and add signals to be simulated.**
    
     *  For each signal that you want to add to the simulation, right click on the signal name in the *Objects* window and select *Add* | *To Wave* | *Selected Signal*. Typically, you would want to add all inputs and outputs. A waveform window will appear in the work area.
     *  Alternatively, you can add a range of signals at once by selecting the 1st signal and then, while holding down the <shift>, select the last signal in the range. Then right click in the selected signal region and select *Add* | *To Wave* | *Selected Signals*. A waveform window will appear in the work area.
     *  When all signals are selected, expand the Wave window.
     *  If the Wave window is not floating above the ModelSim main screen, use the top left icon in the *wave* window to *undock* the window. Expand the detached window.  
          
        
 *  **Enter signal values using force.**
    
     *  To enter a signal value on a step by step basis, select an input signal and right click on the pop-up; select *Force* and for *value* enter either 0 or 1. \[*Kind* should be *freeze*, *delay* should be *0*, *cancel after* should be blank.\] Do this for all input signals.
     *  In the tool icons, find the window that contains the period of the signal, e.g. 100ns. Immediately to the right of that window will be the *run simulation* icon (looks like a page with a blue down arrow beside it). Select *run simulation*. You should see the inputs that you entered and the outputs from your system on the waveform. The period of the run will correspond to the time in the period window. All signals should be green. If any signals are red, then one or more of the inputs was not specified.
     *  Change one of the input signals. Select an input signal and right click on the pop-up; select *Force* and for *value* change the 0/1 to 1/0. Select *run simulation*.
     *  Repeat until all combinations have been tested.
     *  Immediately to the left of the signal period window is the *restart simulation* icon. Selecting *restart* will erase all signal values entered.

转载于:https://www.cnblogs.com/quxiaoxia/p/3922314.html

[Quartus_ II Introduction Using Schematic Designs]: ftp://ftp.altera.com/up/pub/Altera_Material/12.0/Tutorials/Schematic/Quartus_II_Introduction.pdf