简单的nios II 流水灯硬件部分

矫情吗；* 2021-12-03 05:57 510阅读 0赞

**声明：本文为灵. yāo编写，版权****所有，欢迎学习讨论，如需转载请标明出处****[http://www.cnblogs.com/China\_memory][http_www.cnblogs.com_China_memory]**

简单的nios II 流水灯

贴出来和大家分享一下，文中借鉴来自互联网和书籍

硬件平台：康草EP2C5-V5

FPGA :EP2C5Q208C8N

SDRAM:K4S641632k

Flash:JS28F640

4位led

软件平台：Microsoft Windows xp Professional sp3(深度D版)

Quartus II 10.0 SP1 Build: 262** **

Nios II IDE 10.0 SP1 Build: 262

一、硬件  
1.新建Quartus 工程

![2010092811065923.png][]

Next>   Next>

![2010092811083565.png][]

Finish

2.构建sopc

2.1调出SOPC Builder

![2010092811131282.png][]

2.2建立系统

![2010092811202774.png][]  
2.2.1配置系统时钟

![2010092811235370.png][]

2.3查找并添加Nios II processor

![2010092811310737.png][]

cup配置

弄个高速的cup玩玩，按个人喜好配置。

![2010092811561955.png][]

Next>

![2010092812005843.png][]

如此配置原因是AVIC(马瑞)博客中提到“NIOS II下关于无法进行寄存器操作PIO的问题解析”

Next>

JTAG Debug Module 选择 Leve 1

Finish

2.4添加SDRAM Controller

![2010092813372151.png][]

康草EP2c5-v5上SDRAM是SAMSUNG K4S641632K

其Memory Profile配置如下

![2010092813443744.png][]

Timing时序配置

![2010092813463165.png][]

2.5 添加Flash

由于altra采用具有avalon接口的CFI控制器与Flash相连，所以添加Flash Memory (Common Flash Interface)

![2010092813534452.png][]

康草EP2c5-v5上Flash是JS28F640 其地址位宽23，数据位宽8位，Attributes 配置如下

![2010092813585513.png][]

Next>

其Triming配置

![2010092814025440.png][]

Finish

然后系统提示

Error: cfi\_flash\_0: cfi\_flash\_0.s1 must be connected to an Avalon-MM Tristate master

这是因为CFI控制器需要Avalon-MM Tristate master

2.5添加Avalon-MM Tristate Brideg

![2010092814093490.png][]

默认选择

![2010092814110975.png][]

Finish

由于CFI需要Avalon-MM Tristate master，看到图中的小叉叉没，表示没有连接，我们要将他们连接起来

![2010092814161175.png][]

当鼠标靠近那个小叉叉时时，tristate master会自动连向我们刚才添加的CFI，并且连接点是一个小白点，表示连接可以，鼠标拿开时他们又断开了![2010092814233258.png][]

这时我们只需点击那个小白点，他们就连接起来了。

![2010092814235512.png][]

连接好了，是不是很有趣。

2.添加 JTAG UART

JTAG UART可以用于观察调试数据，调试时可设置将数据发送到Nios IDE调试界面，便于程序调试

![2010092814290833.png][]

默认配置

![2010092814302142.png][]

Finish

2.添加PIO

PIO用于输入输出

![2010092814333072.png][]

配置为only output，康草EP2C5-V5板上只有4个led

![2010092814363591.png][]

Finish

添加system ID

![2010092815470451.png][]

此组件不用配置

![2010092815483575.png][]

Finish

至此，添加组建基本完成，还需设置

将组件名字改成自己需要的名字

![2010092815191895.png][]

但组件名不能和工程名相同，不然Quartus编译时会出现"Project too complex: hierarchy path is too long”的错误

我改成了如下图

![2010092815205176.png][]

现在设置CPU 的 reset vector 和 Exception Vector

双击CPU，点击 reset vector   Memory 下拉窗 选择 cfi\_flash

点击 Exception Vector memory 下拉窗 选择 sdram

![2010092815265244.png][]

Finish

然后锁定flash地址，将flash存储器地址锁定为0，cup复位后从flash内代码开始执行

点击cfi\_flash Base 栏中的小锁标志

![2010092815320541.png][]

点击后，该小锁变黑，表示锁定了。

然后自动分配地址，中断号

点击system 下 Auto-Assign Base Addresses

![2010092815351578.png][]

再点击system 下 Auto-Assign Base IRQs

检查无错误，无警告。

![2010092815383557.png][]

至此，sopc配置已经完成

点击Next，配置是否产生仿真文件

点击Generate

Save

系统开始编译了，编译较慢，需等较长的时间，可以远眺一下，放松一下眼睛，感谢Altera为广大电子工程师考虑，提醒大家长时间盯电脑后，需要让眼睛休息一下，这就是休息时间。呵呵

提示Info: System generation was successful.

![2010092815553844.png][]

成功

现在Exit，回到Quartus II

New 一个 Block Diagram/Schematic File

![2010092816004016.png][]

双击空白处，添加刚才用sopc buider 建立的 system\_led

再添加 altpll 锁相环

![2010092816035294.png][]

板上时钟50Mhz

![2010092816135456.png][]

取消全部

![2010092816155728.png][]

clk0设置

![2010092816175676.png][]

clk1设置

clk1用于驱动SDRAM，需要-75dge的相差

![2010092816195352.png][]

Finish

将altpll与system\_led相连，并generation pins，将inclk0改为clk，c1改为zs\_clk\_from\_the\_sdram

注意generation pins时，有些引脚名会在末尾产生多余的一个空格，如果引脚配置不成功的话，需要检查一下generation 的pin name是不是多了一个空格

![2010092816263328.png][]

保存为led.bdf加入工程

新建tcl脚本文件，配置引脚

以下为本工程EP2C5-V5引脚配置脚本

\#Setup.tcl  
\# Setup pin setting for EP2C5 main board   
\# nios led  
set\_global\_assignment -name RESERVE\_ALL\_UNUSED\_PINS "AS INPUT TRI-STATED"  
set\_global\_assignment -name ENABLE\_INIT\_DONE\_OUTPUT OFF

set\_location\_assignment PIN\_23 -to clk  
set\_location\_assignment PIN\_56 -to reset\_n  
\#led  
set\_location\_assignment PIN\_6 -to out\_port\_from\_the\_led\_pio\\\[0\\\]  
set\_location\_assignment PIN\_5 -to out\_port\_from\_the\_led\_pio\\\[1\\\]  
set\_location\_assignment PIN\_3 -to out\_port\_from\_the\_led\_pio\\\[2\\\]  
set\_location\_assignment PIN\_4 -to out\_port\_from\_the\_led\_pio\\\[3\\\]  
\#flash  
set\_location\_assignment PIN\_201 -to select\_n\_to\_the\_cfi\_flash  
set\_location\_assignment PIN\_168 -to read\_n\_to\_the\_cfi\_flash  
set\_location\_assignment PIN\_165 -to write\_n\_to\_the\_cfi\_flash

set\_location\_assignment PIN\_181 -to address\_to\_the\_cfi\_flash\\\[0\\\]  
set\_location\_assignment PIN\_193 -to address\_to\_the\_cfi\_flash\\\[1\\\]  
set\_location\_assignment PIN\_192 -to address\_to\_the\_cfi\_flash\\\[2\\\]  
set\_location\_assignment PIN\_191 -to address\_to\_the\_cfi\_flash\\\[3\\\]  
set\_location\_assignment PIN\_189 -to address\_to\_the\_cfi\_flash\\\[4\\\]  
set\_location\_assignment PIN\_188 -to address\_to\_the\_cfi\_flash\\\[5\\\]  
set\_location\_assignment PIN\_187 -to address\_to\_the\_cfi\_flash\\\[6\\\]  
set\_location\_assignment PIN\_185 -to address\_to\_the\_cfi\_flash\\\[7\\\]  
set\_location\_assignment PIN\_197 -to address\_to\_the\_cfi\_flash\\\[8\\\]  
set\_location\_assignment PIN\_195 -to address\_to\_the\_cfi\_flash\\\[9\\\]  
set\_location\_assignment PIN\_199 -to address\_to\_the\_cfi\_flash\\\[10\\\]  
set\_location\_assignment PIN\_198 -to address\_to\_the\_cfi\_flash\\\[11\\\]  
set\_location\_assignment PIN\_200 -to address\_to\_the\_cfi\_flash\\\[12\\\]  
set\_location\_assignment PIN\_205 -to address\_to\_the\_cfi\_flash\\\[13\\\]  
set\_location\_assignment PIN\_203 -to address\_to\_the\_cfi\_flash\\\[14\\\]  
set\_location\_assignment PIN\_207 -to address\_to\_the\_cfi\_flash\\\[15\\\]  
set\_location\_assignment PIN\_206 -to address\_to\_the\_cfi\_flash\\\[16\\\]  
set\_location\_assignment PIN\_208 -to address\_to\_the\_cfi\_flash\\\[17\\\]  
set\_location\_assignment PIN\_14 -to address\_to\_the\_cfi\_flash\\\[18\\\]  
set\_location\_assignment PIN\_13 -to address\_to\_the\_cfi\_flash\\\[19\\\]  
set\_location\_assignment PIN\_12 -to address\_to\_the\_cfi\_flash\\\[20\\\]  
set\_location\_assignment PIN\_11 -to address\_to\_the\_cfi\_flash\\\[21\\\]  
set\_location\_assignment PIN\_10 -to address\_to\_the\_cfi\_flash\\\[22\\\]

set\_location\_assignment PIN\_180 -to data\_to\_and\_from\_the\_cfi\_flash\\\[0\\\]  
set\_location\_assignment PIN\_179 -to data\_to\_and\_from\_the\_cfi\_flash\\\[1\\\]  
set\_location\_assignment PIN\_176 -to data\_to\_and\_from\_the\_cfi\_flash\\\[2\\\]  
set\_location\_assignment PIN\_175 -to data\_to\_and\_from\_the\_cfi\_flash\\\[3\\\]  
set\_location\_assignment PIN\_173 -to data\_to\_and\_from\_the\_cfi\_flash\\\[4\\\]  
set\_location\_assignment PIN\_171 -to data\_to\_and\_from\_the\_cfi\_flash\\\[5\\\]  
set\_location\_assignment PIN\_170 -to data\_to\_and\_from\_the\_cfi\_flash\\\[6\\\]  
set\_location\_assignment PIN\_169 -to data\_to\_and\_from\_the\_cfi\_flash\\\[7\\\]

\#SDRAM  
set\_location\_assignment PIN\_31 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[0\\\]  
set\_location\_assignment PIN\_30 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[1\\\]  
set\_location\_assignment PIN\_33 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[2\\\]  
set\_location\_assignment PIN\_35 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[3\\\]  
set\_location\_assignment PIN\_34 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[4\\\]  
set\_location\_assignment PIN\_37 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[5\\\]  
set\_location\_assignment PIN\_39 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[6\\\]  
set\_location\_assignment PIN\_41 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[7\\\]  
set\_location\_assignment PIN\_77 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[8\\\]  
set\_location\_assignment PIN\_60 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[9\\\]  
set\_location\_assignment PIN\_59 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[10\\\]  
set\_location\_assignment PIN\_58 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[11\\\]  
set\_location\_assignment PIN\_57 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[12\\\]  
set\_location\_assignment PIN\_45 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[13\\\]  
set\_location\_assignment PIN\_48 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[14\\\]  
set\_location\_assignment PIN\_47 -to zs\_dq\_to\_and\_from\_the\_sdram\\\[15\\\]

set\_location\_assignment PIN\_82 -to zs\_addr\_from\_the\_sdram\\\[0\\\]  
set\_location\_assignment PIN\_86 -to zs\_addr\_from\_the\_sdram\\\[1\\\]  
set\_location\_assignment PIN\_88 -to zs\_addr\_from\_the\_sdram\\\[2\\\]  
set\_location\_assignment PIN\_87 -to zs\_addr\_from\_the\_sdram\\\[3\\\]  
set\_location\_assignment PIN\_70 -to zs\_addr\_from\_the\_sdram\\\[4\\\]  
set\_location\_assignment PIN\_69 -to zs\_addr\_from\_the\_sdram\\\[5\\\]  
set\_location\_assignment PIN\_68 -to zs\_addr\_from\_the\_sdram\\\[6\\\]  
set\_location\_assignment PIN\_67 -to zs\_addr\_from\_the\_sdram\\\[7\\\]  
set\_location\_assignment PIN\_72 -to zs\_addr\_from\_the\_sdram\\\[8\\\]  
set\_location\_assignment PIN\_75 -to zs\_addr\_from\_the\_sdram\\\[9\\\]  
set\_location\_assignment PIN\_84 -to zs\_addr\_from\_the\_sdram\\\[10\\\]  
set\_location\_assignment PIN\_74 -to zs\_addr\_from\_the\_sdram\\\[11\\\]

set\_location\_assignment PIN\_81 -to zs\_ba\_from\_the\_sdram\\\[0\\\]  
set\_location\_assignment PIN\_80 -to zs\_ba\_from\_the\_sdram\\\[1\\\]

set\_location\_assignment PIN\_40 -to zs\_dqm\_from\_the\_sdram\\\[0\\\]  
set\_location\_assignment PIN\_61 -to zs\_dqm\_from\_the\_sdram\\\[1\\\]

set\_location\_assignment PIN\_76 -to zs\_cs\_n\_from\_the\_sdram  
set\_location\_assignment PIN\_46 -to zs\_ras\_n\_from\_the\_sdram  
set\_location\_assignment PIN\_43 -to zs\_cas\_n\_from\_the\_sdram  
set\_location\_assignment PIN\_44 -to zs\_we\_n\_from\_the\_sdram  
set\_location\_assignment PIN\_63 -to zs\_cke\_from\_the\_sdram  
set\_location\_assignment PIN\_64 -to zs\_clk\_from\_the\_sdram

保存后，将led.bdf set as top-Leve Entity

然后run刚才的.tcl脚本文件

引脚配置成功

![2010092816415055.png][]

最后Start Compilation

![2010092816505128.png][]

成功，下载到fpga实验板，硬件部分就完成了。

转载于:https://www.cnblogs.com/China\_memory/archive/2010/09/28/1837707.html

[http_www.cnblogs.com_China_memory]: http://www.cnblogs.com/China_memory
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