Verilog/SystemVerilog/SystemC的开源项目

刺骨的言语ヽ痛彻心扉 2021-10-26 21:31 897阅读 0赞

[http://shiori.blog.edu.cn/2006/22618.html][http_shiori.blog.edu.cn_2006_22618.html]

**　　学EDA的同学可以通过开源提高自己**

前两天和同学讨论说实验室里研究EDA的同学可以或参与或解读一些开源的项目来提高自己。

*  **开源之于EDA**

如今的电子行业已经离不开各种各样的EDA软件了。EDA(Electronic Design Automation)可以理解为供电子的企业级软件，为工程师提供服务的计算机辅助设计工具。如果你画过PCB板，或许你对这个名词就会有一个初步的认识。然而EDA工具远不止板级设计工具，这个名词现在更多地知道集成电路(IC)设计中使用的工具。从代码输入，综合，仿真，验证，布局布线，版图设计……它渗透到集成电路设计的每个环节。宏观的人和微观的晶体管之间如何沟通? 那就是通过EDA工具了。我们期望能够高效地沟通，所以希望EDA工具越来越强大，只可惜它们的表现多少有些差强人意！

7月底在美国举行的2006年DAC上Cadence的前CEO，Joe Costello说在开源并不适合EDA行业，原因是从事这个行业的人太少，而开源需要大量散落在网络各个角落的工程师共同开发与推进。EDA市场是商业软件的天下，Cadence，Sysnopsys，Mentor Graphics和Magma占有了绝大部分的市场份额。问题在于这个市场到达40亿美元就有些停滞不前了。 全球其实有一陀陀的初创公司(Start-up companies)，有的成长得也还不错。然而很多人断言如Cadence等巨擎的地位不会被动摇。其实很多初创公司最后的结局就是被这些巨擎收购，前两天刚看到消息说一家台湾的EDA公司被Mentor收购了。这让我想起同学说“微软不用打败对手，只需要收买对手……”，呵呵！

全世界从事EDA软件开发的人有多少，我还不清楚！好像Synopsys全球也就千把人。不知道这样算来纯EDA软件开发人员全世界有多少，可能和很多其他领域的软件开发人员相比，真的很少。但我想全世界电子工程师的数量很多。美国每年高校培养70,000+70,000的电子工程师。中国、印度的数量现在更多。我想不能忽视他们在推动EDA发展上的力量。他们是EDA的用户，他们头脑中有这来自设计的第一手的需求！

*  **SourceForge上搜到的关于Verilog/SystemVerilog/SystemC的开源项目**

我似乎有点扯了，闲话不多说。EDA相关的开源项目很多，由于我最近关心硬件相关的编程和建模语言，因此搜索了一下Verilog，SystemVerilog，SystemC相关的开源项目：

其实搜到了很多，但是只列出了目前至少有一个版本available的项目，有几个项目前两天刚出了版本。罗列如下，以飨读者！

**A: Verilog相关：**  
  
·**Eclipse Verilog editor**  
[http://sourceforge.net/projects/veditor][http_sourceforge.net_projects_veditor]  
[http://icarus.com/eda/verilog/][http_icarus.com_eda_verilog]  
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

·**Icarus Verilog**  
[http://sourceforge.net/projects/iverilog][http_sourceforge.net_projects_iverilog]  
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2001 plus extensions.

·**Source Navigator for Verilog**  
[http://sourceforge.net/projects/snverilog][http_sourceforge.net_projects_snverilog]  
[http://sources.redhat.com/sourcenav][http_sources.redhat.com_sourcenav]  
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language.

·**Icarus Verilog Test Suite**  
[http://sourceforge.net/projects/ivtest][http_sourceforge.net_projects_ivtest]  
Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com.

·**Vtracer**  
[http://sourceforge.net/projects/vtracer][http_sourceforge.net_projects_vtracer]  
VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.

·**VeriWell Verilog Simulator**  
[http://sourceforge.net/projects/veriwell][http_sourceforge.net_projects_veriwell]  
VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell \*is\* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

·**PVSim Verilog Simulator**  
[http://sourceforge.net/projects/pvsim][http_sourceforge.net_projects_pvsim]  
PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor's Verilog mode and features a fast compile-simulate-display cycle.

·**Verilog Construction Toolkit**  
[http://sourceforge.net/projects/vct][http_sourceforge.net_projects_vct]  
The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create  and or modify verilog cell-based structural netlists.

·**Verilog Netlist Viewer / Editor**  
[http://sourceforge.net/projects/netedit][http_sourceforge.net_projects_netedit]  
The purpose of this tool is creation of tcl/tk - based environment for convenient Verilog netlist viewing and editing. This tool will allow development of TCL scripts in order to make structural changes in verilog netlist.

·**SystemC to Verilog RTL converter**  
[http://sourceforge.net/projects/sysc2ver][http_sourceforge.net_projects_sysc2ver]  
sysc2ver - SystemC to Verilog RTL converter

·**FPGA C Compiler**  
[http://sourceforge.net/projects/fpgac][http_sourceforge.net_projects_fpgac]  
FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info on Home Page.

·**vIDE**  
[http://sourceforge.net/projects/vlogide][http_sourceforge.net_projects_vlogide]  
vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.

·**Covered**  
[http://sourceforge.net/projects/covered][http_sourceforge.net_projects_covered]  
Covered is a Verilog code-coverage utility using VCD/LXT style dumpfiles and the design to generate line, toggle, combinational logic and FSM state/arc coverage reports. Covered also contains a built-in race condition checker and GUI report viewer.

·**veri-indent**  
[http://sourceforge.net/projects/veriindent][http_sourceforge.net_projects_veriindent]  
Veri-indent is a verilog source code Parser,Analyzer and Beautifier. (similar to c 'indent' , but more than that). Verilog source can be formatted and Symbol table, list of registers,wires,pli calls in source code can be extracted.

·**Teal**  
[http://sourceforge.net/projects/teal][http_sourceforge.net_projects_teal]  
TEAL - C++ multithreaded library to verfiy verilog designs

·**Reed-Solomon Core Compiler**  
[http://sourceforge.net/projects/rstk][http_sourceforge.net_projects_rstk]  
RSTK is a C language program that generates Reed-Solomon HDL source code modules that  can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis  tools.

·**XSpiceHDL**  
[http://sourceforge.net/projects/xspicehdl][http_sourceforge.net_projects_xspicehdl]  
XSpiceHDL, a mixed-mode XSpice-Verilog HDL co-simulation environment incorporating GUI schematic capture, modified XSpice3f5 based engine and TCP inter-process communications via CodeModel and VPI DLL, written in C++ using the wxWindows API.

**B:** **SystemVerilog相关：(真是少得可怜)**  
  
·**HDLObf**  
[http://sourceforge.net/projects/hdlobf][http_sourceforge.net_projects_hdlobf]  
HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog. Support will be added for VHDL/SystemC in future.

**C: SystemC相关：**  
  
·**Open SystemC Initiative (OSCI)**  
[http://sourceforge.net/projects/systemc][http_sourceforge.net_projects_systemc]  
The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification

·**FERMAT SystemC Parser**  
[http://sourceforge.net/projects/systemcxml][http_sourceforge.net_projects_systemcxml]  
FERMAT's SystemC Parser using Doxygen and Xerces-C++ XML

·**SCLive**  
[http://sourceforge.net/projects/sclive][http_sourceforge.net_projects_sclive]  
SCLive is a modular Linux-Live Distribution dedicated to the OSCI SystemC simulator and it's associated libraries. The distribution provides a fully working environement including a simulator kernel, wavefom viewer, IDE, tutorials and more.

·**GreenSocs**  
[http://sourceforge.net/projects/greensocs][http_sourceforge.net_projects_greensocs]  
[http://www.greensocs.com][http_www.greensocs.com]  
To develop SystemC infrustructure, basic IP, patches and add on library code for eventual standerdization. The GreenSocs project is made up of a number of contributions (sub projects). Please visit [www.greensocs.com][http_www.greensocs.com] for more information.

[www.opencores.org][]是IC行业有名的开源网站，等我有空了再到那里去转转，说不定会有不少收获！

Trackback: http://tb.blog.csdn.net/TrackBack.aspx?PostId=1057134

\[ 收藏到我的网摘\]   phixcoco发表于 2006年08月13日 10:48:00

\--> function hide()\{showComment();\}

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这么来看，目前这个市场与社区是需要培育的，但不知道会等到哪一天：）

[\#][Link 4]    [phixcoco][] 发表于2006-08-14 13:20:00  IP: 10.212.43.243, 10.212.43.\*

电子设计对于EDA工具的需求是很旺盛的！  
  
但我作为EDA工具的消费者总觉得工具不够强大，又贵；  
而EDA工具商们总是宣传说自己设计了多么好的软件，然后以高价叫卖！  
  
不过EDA这个方向的开源社区的确需要培养  
现在有人在Eclipse的平台上设计嵌入式设计的插件~使得Eclipse可以成为电子设计的平台，也得到了一些厂商的支持  
  
EDA工具触及设计的各个角落，功能需求五花八门~  
我觉得和物理设计相关的领域可能开源软件比较难进入，如和制造相关的EDA工具，因为开源的设计者无法与芯片制造企业合作得到很多物理制造的参数，没法为工艺建模，也无法得到大量样本的工艺库数据。其他很多方面是可以有所作为的！  
  
特别是抓住新兴的功能需求，否则总是开发某种格式的读取查看工具、抑或代码编写和仿真工具就只能是模仿商用软件的份（不过如果做的好也是很有价值的）

转载于:https://www.cnblogs.com/asic/archive/2011/05/22/2053245.html

[http_shiori.blog.edu.cn_2006_22618.html]: http://shiori.blog.edu.cn/2006/22618.html
[http_sourceforge.net_projects_veditor]: http://sourceforge.net/projects/veditor
[http_icarus.com_eda_verilog]: http://icarus.com/eda/verilog/
[http_sourceforge.net_projects_iverilog]: http://sourceforge.net/projects/iverilog
[http_sourceforge.net_projects_snverilog]: http://sourceforge.net/projects/snverilog
[http_sources.redhat.com_sourcenav]: http://sources.redhat.com/sourcenav
[http_sourceforge.net_projects_ivtest]: http://sourceforge.net/projects/ivtest
[http_sourceforge.net_projects_vtracer]: http://sourceforge.net/projects/vtracer
[http_sourceforge.net_projects_veriwell]: http://sourceforge.net/projects/veriwell
[http_sourceforge.net_projects_pvsim]: http://sourceforge.net/projects/pvsim
[http_sourceforge.net_projects_vct]: http://sourceforge.net/projects/vct
[http_sourceforge.net_projects_netedit]: http://sourceforge.net/projects/netedit
[http_sourceforge.net_projects_sysc2ver]: http://sourceforge.net/projects/sysc2ver
[http_sourceforge.net_projects_fpgac]: http://sourceforge.net/projects/fpgac
[http_sourceforge.net_projects_vlogide]: http://sourceforge.net/projects/vlogide
[http_sourceforge.net_projects_covered]: http://sourceforge.net/projects/covered
[http_sourceforge.net_projects_veriindent]: http://sourceforge.net/projects/veriindent
[http_sourceforge.net_projects_teal]: http://sourceforge.net/projects/teal
[http_sourceforge.net_projects_rstk]: http://sourceforge.net/projects/rstk
[http_sourceforge.net_projects_xspicehdl]: http://sourceforge.net/projects/xspicehdl
[http_sourceforge.net_projects_hdlobf]: http://sourceforge.net/projects/hdlobf
[http_sourceforge.net_projects_systemc]: http://sourceforge.net/projects/systemc
[http_sourceforge.net_projects_systemcxml]: http://sourceforge.net/projects/systemcxml
[http_sourceforge.net_projects_sclive]: http://sourceforge.net/projects/sclive
[http_sourceforge.net_projects_greensocs]: http://sourceforge.net/projects/greensocs
[http_www.greensocs.com]: http://www.greensocs.com/
[www.opencores.org]: http://www.opencores.org/
[Link 1]: http://tag.csdn.net/tag/%E5%BC%80%E6%BA%90
[Link 2]: http://blog.csdn.net/phixcoco/archive/2006/08/13/1057134.aspx#473975
[Link 3]: http://blog.csdn.net/futurelight
[Link 4]: http://blog.csdn.net/phixcoco/archive/2006/08/13/1057134.aspx#474083
[phixcoco]: http://blog.csdn.net/phixcoco