VHDL——74LS138译码器

- 日理万妓 2023-10-04 10:56 8阅读 0赞

1.功能描述  
![20210415230822466.png][]  
功能描述：该3-8译码器有六个输入端：S1,S2,S3为控制信号，a0,a1,a2为三个输入信号。一个输出端口y为八位总线，表示译码结果。

2.真值表  
![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L20wXzU0MzU1MTcy_size_16_color_FFFFFF_t_70][]

3.VHDL语言  
3.1case语句

library ieee;
    use ieee.std_logic_1164.all;
    
    entity decode38 is
        port(a,b,c,g1,g2a,g2b : in std_logic;
    	     y : out std_logic_vector(7 downto 0));
    end decode38;
    
    architecture rtl of decode38 is
    signal indata : std_logic_vector(2 downto 0);
    begin
        indata <= c&b&a;
    process(indata,g1,g2a,g2b)
    begin
        if(g1 = '1' and g2a = '0' and g2b = '0')then
    	 case indata is
    	 when "000" => y <= "11111110";
    	 when "001" => y <= "11111101";
    	 when "010" => y <= "11111011";
    	 when "011" => y <= "11110111";
    	 when "100" => y <= "11101111";
    	 when "101" => y <= "11011111";
    	 when "110" => y <= "10111111";
    	 when "111" => y <= "01111111";
    	 when others => y <= null;      --输入其他数据，y指向空
    	 end case;
        else
    	 y <= "11111111";
    	 end if;
    end process;
    end rtl;

3.2if语句

library ieee;
    use ieee.std_logic_1164.all;
    
    entity decode38 is
        port(a,b,c,g1,g2a,g2b : in std_logic;
    	     y : out std_logic_vector(7 downto 0));
    end decode38;
    
    architecture rtl of decode38 is
    signal indata : std_logic_vector(2 downto 0);
    begin
        indata <= c&b&a;
    process(indata,g1,g2a,g2b)
    begin
        if(g1 = '1' and g2a = '0' and g2b = '0')then
    	   if(indata = "000") then y <= "11111110";
    	   elsif(indata = "001") then y <= "11111101";
    	   elsif(indata = "010") then y <= "11111011";
    	   elsif(indata = "011") then y <= "11110111";
    	   elsif(indata = "100") then y <= "11101111";
    	   elsif(indata = "101") then y <= "11011111";
    	   elsif(indata = "110") then y <= "10111111";
    	   elsif(indata = "111") then y <= "01111111";
    	   else
    	   y <= null;
    	   end if;
        else
    	 y <= "11111111";
    	 end if;
    end process;
    end rtl;

[20210415230822466.png]: https://img-blog.csdnimg.cn/20210415230822466.png
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L20wXzU0MzU1MTcy_size_16_color_FFFFFF_t_70]: https://img-blog.csdnimg.cn/20210415231207832.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L20wXzU0MzU1MTcy,size_16,color_FFFFFF,t_70