GGC 编译Intrinsic

太过爱你忘了你带给我的痛 2021-11-09 12:38 285阅读 0赞

[http://www.linuxjournal.com/content/introduction-gcc-compiler-intrinsics-vector-processing?page=0,1][http_www.linuxjournal.com_content_introduction-gcc-compiler-intrinsics-vector-processing_page_0_1]

[http://stackoverflow.com/questions/7156908/sse-intrinsic-functions-reference][http_stackoverflow.com_questions_7156908_sse-intrinsic-functions-reference]

Table 1. GCC Command-Line Options to Generate SIMD Code

<table> 
 <tbody> 
 <tr> 
 <th>Processor/</th> 
 <th>&nbsp;</th> 
 <th>Options</th> 
 </tr> 
 <tr> 
 <td>X86/MMX/SSE1/SSE2</td> 
 <td>-mfpmath=sse -mmmx -msse -msse2</td> 
 </tr> 
 <tr> 
 <td>ARM Neon</td> 
 <td>-mfpu=neon -mfloat-abi=softfp</td> 
 </tr> 
 <tr> 
 <td>Freescale Altivec</td> 
 <td>-maltivec -mabi=altivec</td> 
 </tr> 
 </tbody> 
</table>

Here are the include files you need:

*  arm\_neon.h - ARM Neon types & intrinsics
 *  altivec.h - Freescale Altivec types & intrinsics
 *  mmintrin.h - X86 MMX
 *  xmmintrin.h - X86 SSE1
 *  emmintrin.h - X86 SSE2

### X86: MMX, SSE, SSE2 Types and Debugging ###

The X86 compatibles with MMX, SSE1 and SSE2 have the following types:

*  MMX: \_\_m64 64 bits of integers broken down as eight 8-bit integers, four 16-bit shorts or two 32-bit integers.
 *  SSE1: \_\_m128 128 bits: four single precision floats.
 *  SSE2: \_\_m128i 128 bits of any size packed integers, \_\_m128d 128 bits: two doubles.

Table 2. Subset of vector operators and intrinsics used in the examples.

<table> 
 <tbody> 
 <tr> 
 <th> Operation </th> 
 <th> Altivec </th> 
 <th> Neon </th> 
 <th> MMX/SSE/SSE2 </th> 
 </tr> 
 <tr> 
 <td> loading </td> 
 <td> vec_ld </td> 
 <td> vld1q_f32 </td> 
 <td> _mm_set_epi16 </td> 
 </tr> 
 <tr> 
 <td> vector </td> 
 <td> vec_splat </td> 
 <td> vld1q_s16 </td> 
 <td> _mm_set1_epi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_splat_s16 </td> 
 <td> vsetq_lane_f32 </td> 
 <td> _mm_set1_pi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_splat_s32 </td> 
 <td> vld1_u8 </td> 
 <td> _mm_set_pi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_splat_s8 </td> 
 <td> vdupq_lane_s16 </td> 
 <td> _mm_load_ps </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_splat_u16 </td> 
 <td> vdupq_n_s16 </td> 
 <td> _mm_set1_ps </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_splat_u32 </td> 
 <td> vmovq_n_f32 </td> 
 <td> _mm_loadh_pi </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_splat_u8 </td> 
 <td> vset_lane_u8 </td> 
 <td> _mm_loadl_pi </td> 
 </tr> 
 <tr> 
 <td> storing </td> 
 <td> vec_st </td> 
 <td> vst1_u8 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> vector </td> 
 <td> &nbsp; </td> 
 <td> vst1q_s16 </td> 
 <td> _mm_store_ps </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vst1q_f32 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vst1_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> add </td> 
 <td> vec_madd </td> 
 <td> vaddq_s16 </td> 
 <td> _mm_add_epi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_mladd </td> 
 <td> vaddq_f32 </td> 
 <td> _mm_add_pi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_adds </td> 
 <td> vmlaq_n_f32 </td> 
 <td> _mm_add_ps </td> 
 </tr> 
 <tr> 
 <td> subtract </td> 
 <td> vec_sub </td> 
 <td> vsubq_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> multiply </td> 
 <td> vec_madd </td> 
 <td> vmulq_n_s16 </td> 
 <td> _mm_mullo_epi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_mladd </td> 
 <td> vmulq_s16 </td> 
 <td> _mm_mullo_pi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vmulq_f32 </td> 
 <td> _mm_mul_ps </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vmlaq_n_f32 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> arithmetic </td> 
 <td> vec_sra </td> 
 <td> vshrq_n_s16 </td> 
 <td> _mm_srai_epi16 </td> 
 </tr> 
 <tr> 
 <td> shift </td> 
 <td> vec_srl </td> 
 <td> &nbsp; </td> 
 <td> _mm_srai_pi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_sr </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> byte </td> 
 <td> vec_perm </td> 
 <td> vtbl1_u8 </td> 
 <td> _mm_shuffle_pi16 </td> 
 </tr> 
 <tr> 
 <td> permutation </td> 
 <td> vec_sel </td> 
 <td> vtbx1_u8 </td> 
 <td> _mm_shuffle_ps </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_mergeh </td> 
 <td> vget_high_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_mergel </td> 
 <td> vget_low_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vdupq_lane_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vdupq_n_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vmovq_n_f32 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vbsl_u8 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> type </td> 
 <td> vec_cts </td> 
 <td> vmovl_u8 </td> 
 <td> _mm_packs_pu16 </td> 
 </tr> 
 <tr> 
 <td> conversion </td> 
 <td> vec_unpackh </td> 
 <td> vreinterpretq_s16_u16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_unpackl </td> 
 <td> vcvtq_u32_f32 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_cts </td> 
 <td> vqmovn_s32 </td> 
 <td> _mm_cvtps_pi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> vec_ctu </td> 
 <td> vqmovun_s16 </td> 
 <td> _mm_packus_epi16 </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vqmovn_u16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vcvtq_f32_s32 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vmovl_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vmovq_n_f32 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> vector </td> 
 <td> vec_pack </td> 
 <td> vcombine_u16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> combination </td> 
 <td> vec_packsu </td> 
 <td> vcombine_u8 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> vcombine_s16 </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> maximum </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> _mm_max_ps </td> 
 </tr> 
 <tr> 
 <td> minimum </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> _mm_min_ps </td> 
 </tr> 
 <tr> 
 <td> vector </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> _mm_andnot_ps </td> 
 </tr> 
 <tr> 
 <td> logic </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> _mm_and_ps </td> 
 </tr> 
 <tr> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> _mm_or_ps </td> 
 </tr> 
 <tr> 
 <td> rounding </td> 
 <td> vec_trunc </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 </tr> 
 <tr> 
 <td> misc </td> 
 <td> &nbsp; </td> 
 <td> &nbsp; </td> 
 <td> _mm_empty </td> 
 </tr> 
 </tbody> 
</table>

#### Check Processor at Runtime ####

Next, your code should check your processor at runtime to see if you have vector support for it. If you don't have a vector code path for that processor, fall back to your scalar code. If you have vector support, and the vector support is faster, use the vector code path. Test processor features on X86 with the cpuid instruction from <cpuid.h>. (You saw examples of that in samples/simple/x86/\*c.) We couldn't find something that well established for Altivec and Neon, so the examples there parse /proc/cpuinfo. (Serious code might insert a test SIMD instruction. If the processor throws a SIGILL signal when it encounters that test instruction, you do not have that feature.)

### Summary ###

In summary, GCC offers intrinsics that allow you to get more from your processor without the work of going all the way to assembly. We have covered basic types and some of the vector math functions. When you use intrinsics, make sure you test thoroughly. Test for speed and correctness against a scalar version of your code. Different features of each processor and how well they operate means that this is a wide open field. The more effort you put into it, the more you will get out.

### References: ###

The GCC include files that map intrinsics to compiler built-ins (eg arm\_neon.h) and the GCC info pages that explain those built-ins:

[http://gcc.gnu.org/onlinedocs/gcc/Target-Builtins.html][http_gcc.gnu.org_onlinedocs_gcc_Target-Builtins.html]  
  
  
[http://ds9a.nl/gcc-simd/][http_ds9a.nl_gcc-simd]  
[http://softpixel.com/~cwright/programming/simd/index.php][http_softpixel.com_cwright_programming_simd_index.php]  
  
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0002a/BABCJFDG.html][http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dht0002a_BABCJFDG.html]  
[http://www.arm.com/products/processors/technologies/neon.php][http_www.arm.com_products_processors_technologies_neon.php]  
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0002a/ch01s04s02.html][http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dht0002a_ch01s04s02.html]  
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0205j/BABGHIFH.html][http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0205j_BABGHIFH.html]  
  
[http://www.tommesani.com/Docs.html][http_www.tommesani.com_Docs.html]  
[http://www.linuxjournal.com/article/7269][http_www.linuxjournal.com_article_7269]  
  
[http://developer.apple.com/hardwaredrivers/ve/sse.html][http_developer.apple.com_hardwaredrivers_ve_sse.html]  
[http://en.wikipedia.org/wiki/Multiplication\_algorithm\#Shift\_and\_add][http_en.wikipedia.org_wiki_Multiplication_algorithm_Shift_and_add]  
[http://www.ibm.com/developerworks/power/library/pa-unrollav1/][http_www.ibm.com_developerworks_power_library_pa-unrollav1]  
[http://en.wikipedia.org/wiki/MMX\_(instruction\_set)][http_en.wikipedia.org_wiki_MMX_instruction_set]  
  
Integrated Performance Primitives  
[http://software.intel.com/en-us/articles/intel-ipp/][http_software.intel.com_en-us_articles_intel-ipp]  
[http://software.intel.com/en-us/articles/non-commercial-software-download/][http_software.intel.com_en-us_articles_non-commercial-software-download]  
  
OpenMAX  
[http://www.khronos.org/developers/resources/openmax][http_www.khronos.org_developers_resources_openmax]  
  
Freescale AltiVec Libs for Linux  
[http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCNWALTVCLIB][http_www.freescale.com_webapp_sps_site_overview.jsp_code_DRPPCNWALTVCLIB]  
  
  
AltiVec TM Technology Programming Interface Manual  
[http://www.freescale.com/files/32bit/doc/ref\_manual/ALTIVECPIM.pdf][http_www.freescale.com_files_32bit_doc_ref_manual_ALTIVECPIM.pdf]  
  
[http://developer.apple.com/hardwaredrivers/ve/instruction\_crossref.html][http_developer.apple.com_hardwaredrivers_ve_instruction_crossref.html]  
  
Ian Ollmann's Altivec Tutorial  
[http://www-linux.gsi.de/~ikisel/reco/Systems/Altivec.pdf][http_www-linux.gsi.de_ikisel_reco_Systems_Altivec.pdf]  
[http://arstechnica.com/civis/viewtopic.php?f=19&t=381165][http_arstechnica.com_civis_viewtopic.php_f_19_t_381165]  
  
RealView Compilation Tools Compiler Reference Guide (especially Appendix E)  
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0348c/index.html][http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0348c_index.html]  
  
RealView Compilation Tools Assembler Guide (esp chapter 5)  
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/index.html][http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0204j_index.html]  
  
Intel C++ Intrinsics Reference  
  
[http://software.intel.com/sites/default/files/m/9/4/c/8/e/18072-347603.pdf][http_software.intel.com_sites_default_files_m_9_4_c_8_e_18072-347603.pdf]

[http_www.linuxjournal.com_content_introduction-gcc-compiler-intrinsics-vector-processing_page_0_1]: http://www.linuxjournal.com/content/introduction-gcc-compiler-intrinsics-vector-processing?page=0,1
[http_stackoverflow.com_questions_7156908_sse-intrinsic-functions-reference]: http://stackoverflow.com/questions/7156908/sse-intrinsic-functions-reference
[http_gcc.gnu.org_onlinedocs_gcc_Target-Builtins.html]: http://gcc.gnu.org/onlinedocs/gcc/Target-Builtins.html
[http_ds9a.nl_gcc-simd]: http://ds9a.nl/gcc-simd/
[http_softpixel.com_cwright_programming_simd_index.php]: http://softpixel.com/~cwright/programming/simd/index.php
[http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dht0002a_BABCJFDG.html]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0002a/BABCJFDG.html
[http_www.arm.com_products_processors_technologies_neon.php]: http://www.arm.com/products/processors/technologies/neon.php
[http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dht0002a_ch01s04s02.html]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0002a/ch01s04s02.html
[http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0205j_BABGHIFH.html]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0205j/BABGHIFH.html
[http_www.tommesani.com_Docs.html]: http://www.tommesani.com/Docs.html
[http_www.linuxjournal.com_article_7269]: http://www.linuxjournal.com/article/7269
[http_developer.apple.com_hardwaredrivers_ve_sse.html]: http://developer.apple.com/hardwaredrivers/ve/sse.html
[http_en.wikipedia.org_wiki_Multiplication_algorithm_Shift_and_add]: http://en.wikipedia.org/wiki/Multiplication_algorithm#Shift_and_add
[http_www.ibm.com_developerworks_power_library_pa-unrollav1]: http://www.ibm.com/developerworks/power/library/pa-unrollav1/
[http_en.wikipedia.org_wiki_MMX_instruction_set]: http://en.wikipedia.org/wiki/MMX_%28instruction_set%29
[http_software.intel.com_en-us_articles_intel-ipp]: http://software.intel.com/en-us/articles/intel-ipp/
[http_software.intel.com_en-us_articles_non-commercial-software-download]: http://software.intel.com/en-us/articles/non-commercial-software-download/
[http_www.khronos.org_developers_resources_openmax]: http://www.khronos.org/developers/resources/openmax
[http_www.freescale.com_webapp_sps_site_overview.jsp_code_DRPPCNWALTVCLIB]: http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCNWALTVCLIB
[http_www.freescale.com_files_32bit_doc_ref_manual_ALTIVECPIM.pdf]: http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPIM.pdf
[http_developer.apple.com_hardwaredrivers_ve_instruction_crossref.html]: http://developer.apple.com/hardwaredrivers/ve/instruction_crossref.html
[http_www-linux.gsi.de_ikisel_reco_Systems_Altivec.pdf]: http://www-linux.gsi.de/~ikisel/reco/Systems/Altivec.pdf
[http_arstechnica.com_civis_viewtopic.php_f_19_t_381165]: http://arstechnica.com/civis/viewtopic.php?f=19&t=381165
[http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0348c_index.html]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0348c/index.html
[http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0204j_index.html]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/index.html
[http_software.intel.com_sites_default_files_m_9_4_c_8_e_18072-347603.pdf]: http://software.intel.com/sites/default/files/m/9/4/c/8/e/18072-347603.pdf